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參數(shù)資料
| 型號(hào)： | ST10R272LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁(yè)數(shù)： | 9/77頁(yè) |
| 文件大?。?/td> | 707K |
| 代理商： | ST10R272LT6 |
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ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
The following table shows the various combinations of pointer post-modification for each of
these 2 new addressing modes. In this document the symbols “[Rwn]” and “[IDXi]” refer to
these addressing modes.
For the CoMACM class of instruction, Parallel Data Move mechanism is implemented. This
class of instruction is only available with double indirect addressing mode. Parallel Data Move
allows the operand pointed by IDXi to be moved to a new location in parallel with the MAC
operation. The write-back address of Parallel Data Move is calculated depending on the post-
modification of IDXi. It is obtained by the reverse operation than the one used to calculate the
new value of IDXi. The following table shows these rules.
Symbol
Mnemonic
Address Pointer Operation
“[IDXi]” stands for
[IDXi](IDXi) ← (IDXi) (no-op)
[IDXi+](IDXi) ← (IDXi) +2 (i=0,1)
[IDXi -]
(IDXi) ← (IDXi) -2 (i=0,1)
[IDXi + QXj](IDXi) ← (IDXi) + (QXj) (i, j =0,1)
[IDXi - QXj](IDXi) ← (IDXi) - (QXj) (i, j =0,1)
“[Rwn]” stands for
[Rwn]
(Rwn)
← (Rwn) (no-op)
[Rwn
+]
(Rwn)
← (Rwn) +2 (n=0-15)
[Rwn-]
(Rwn)
← (Rwn) -2 (k=0-15)
[Rwn
+QRj]
(Rwn)
← (Rwn) + (QRj) (n=0-15;j =0,1)
[Rwn - QRj]
(Rwn)
← (Rwn) - (QRj) (n=0-15; j =0,1)
Table 2 Pointer post-modification combinations for IDXi and Rwn
Instruction
Writeback Address
CoMACM [IDXi+],...
<IDXi-2>
CoMACM [IDXi-],...
<IDXi+2>
CoMACM [IDXi+QXj],...
<IDXi-QXj>
CoMACM [IDXi-QXj],...
<IDXi+QXj>
Table 3 Parallel data move addressing
1
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