參數(shù)資料
型號(hào)： ST10R272LT6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, TQFP-100
文件頁(yè)數(shù)： 42/77頁(yè)
文件大?。?/td> 707K
代理商： ST10R272LT6
47/77
ST10R272L - ELECTRICAL CHARACTERISTICS
16.3.1
CPU Clock Generation Mechanisms
ST10R272L internal operation is controlled by the CPU clock fCPU. Both edges of the CPU
clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external
timing (AC Characteristics) specification therefore depends on the time between two consec-
utive edges of the CPU clock, called “TCL” (see figure below).
The CPU clock signal can be generated by different mechanisms. The duration of TCLs and
their variation (and also the external timing) depends on the fCPU generation mechanism. This
must be considered when calculating ST10R272L timing.
The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13
(P0H.7-5).
Figure 14 CPU clock generation mechanisms
P0.15-13 (P0H.7-5)
CPU frequency
fCPU = fXTAL * F
External clock
input range 10-
50MHz
Notes
111
F
XTAL * 4
2.5 to 12.5 MHz
Default configuration
110
F
XTAL * 3
3.33 to 16.66 MHz
101
F
XTAL * 2
5 to 25 MHz
Table 15 CPU clock generation mechanisms
TCL TCL
fCPU
fXTAL
fCPU
fXTAL
Phase Locked Loop Operation (PLL factor=4)
Direct Clock Drive
TCL
fCPU
fXTAL
Prescaler Operation
1
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