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參數(shù)資料
| 型號： | ST10R272LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 8/77頁 |
| 文件大?。?/td> | 707K |
| 代理商： | ST10R272LT6 |
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ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC)
5.2
MAC Operation
Instruction pipelining
All MAC instructions use the 4-stage pipeline. During each stage the following tasks are
performed:
FETCH: All new instructions are double-word instructions.
DECODE: If required, operand addresses are calculated and the resulting operands are
fetched. IDX and GPR pointers are post-modified if necessary.
EXECUTE: Performs the MAC operation. At the end of the cycle, the Accumulator and the
MAC condition flags are updated if required. Modified GPR pointers are written-back
during this stage, if required.
WRITEBACK: Operand write-back in the case of parallel data move.
Note
At least one instruction which does not use the MAC must be inserted between two
instructions that read from a MAC register. This is because the Accumulator and the
status of the MAC are modified during the Execute stage. The CoSTORE instruction
has been added to allow access to the MAC registers immediately after a MAC
operation.
Address generation
MAC instructions can use some standard ST10 addressing modes such as GPR direct or
#data4 for immediate shift value.
New addressing modes have been added to supply the MAC with two new operands per
instruction cycle. These allow indirect addressing with address pointer post-modification.
Double indirect addressing requires two pointers. Any GPR can be used for one pointer, the
other pointer is provided by one of two specific SFRs IDX0 and IDX1. Two pairs of offset
registers QR0/QR1 and QX0/QX1 are associated with each pointer (GPR or IDXi). The GPR
pointer allows access to the entire memory space, but IDXi are limited to the internal Dual-
Port RAM, except for the CoMOV instruction.
1
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