參數(shù)資料
型號(hào)： ST10R272LT6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, TQFP-100
文件頁數(shù)： 70/77頁
文件大小： 707K
代理商： ST10R272LT6
72/77
ST10R272L - ELECTRICAL CHARACTERISTICS
16.3.7
External Hardware Reset
VDD = 3.3 V ± 0.3 V
VSS = 0 V
TA = -40 to +85 °C
CL = 50 pF
Parameter
Symbol
Max. CPU Clock
= 50 MHz
Variable CPU Clock
1/2TCL = 1 to 50 MHz
Un
it
min.
max.
min.
max.
Sync. RSTIN low time1)
1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available
(about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Con-
figuration is correct on PORT0 (about 50
s for internal pullup devices to load 50 pF from
VILmin to VIHmin).
t70
SR
50
–
4 TCL + 10
–
ns
RSTIN low to internal
reset sequence start
t71
CC
416
4
16
TCL
internal reset sequence,
(RSTIN internally pulled
low)
t72
CC
1024
TCL
RSTIN rising edge to inter-
nal reset condition end
t73
CC
4
6
46TCL
PORT0 system start-up
configuration setup to
RSTIN rising edge 2))
2) The value of bits 0 (EMU), 1 (ADAPT), 13 to 15 (Clock Configuration) are loaded during
hardware reset as long as internal reset signal is active, and have an immediate effect on
the system.
t74
SR
100
–
100
–
ns
PORT0 system start-up
configuration hold after
RSTIN rising edge
t75
SR
1
6
16TCL
Bus signals drive from
internal reset end
t76
CC
0
20
0
20
ns
RSTIN low to signals
release
t77
CC
–
50
–
50
ns
ALE rising edge from inter-
nal reset condition end
t78
CC
8
88TCL
Async. RSTIN low time1
t79
SR
1500
–
1500
–
ns
Table 21 External hardware reset
1
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