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參數(shù)資料
| 型號： | ST10R272LT6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, TQFP-100 |
| 文件頁數(shù)： | 44/77頁 |
| 文件大小： | 707K |
| 代理商： | ST10R272LT6 |
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ST10R272L - ELECTRICAL CHARACTERISTICS
Note
The address float timings in Multiplexed bus mode (t11 and t45) use
instead of
.
Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running
frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then
the PLL is switched off.
Oscillator Watchdog (OWD)
When the clock option selected is direct drive or direct drive with prescaler, in order to provide
a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is
implemented as an additional functionality of the PLL circuitry. This oscillator watchdog
operates as follows:
After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, set bit 4 of
SYSCON register OWDDIS.
When the OWD is enabled, the PLL runs on its free-running frequency and increments the
Oscillator Watchdog counter. On each transition of the XTAL1 pin, the Oscillator Watchdog is
cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows
(after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running
clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU
clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin.
Only a hardware reset can switch the CPU clock source back to direct clock input.
When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL
is switched off to decrease power supply current.
Phase locked loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked
loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by the
factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With
every F’th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. In
this way, fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter
of fCPU which affects individual TCL duration.Therefore, AC characteristics that refer to TCLs
must be calculated using the minimum possible TCL.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL constantly
adjusts its output frequency, it corresponds to the applied input frequency (crystal or
oscillator). The relative deviation for periods of more than one TCL is lower than for one single
TCL. For a period of
N * TCL the minimum value is computed using the corresponding
deviation DN:
TCL
max
1 f
XTAL
DC
max
×
=
TCL
min
TCL
min
TCL
NOM
1
D
N
100
–
()
×
=
D
N
4
N 15
–
() %
[]
±
=
1
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