參數(shù)資料
型號(hào)： ST10R272LT6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 50 MHz, MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, TQFP-100
文件頁數(shù)： 77/77頁
文件大?。?/td> 707K
代理商： ST10R272LT6
9/77
ST10R272L - PIN DESCRIPTION
RSTIN
79
I
5T
Reset Input with Schmitt-Trigger characteristics. Resets the
device when a low level is applied for a specified duration while
the oscillator is running. An internal pullup resistor enables
power-on reset using only a capacitor connected to
VSS. With
a bonding option, the RSTIN pin can also be pulled-down for
512 internal clock cycles for hardware, software or watchdog
timer triggered resets
RSTOUT
80
O
5T
Internal Reset Indication Output. This pin is set to a low level
when the part is executes hardware-, software- or watchdog
timer reset. RSTOUT remains low until the EINIT (end of ini-
tialization) instruction is executed.
NMI
81
I
5S
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine.
If it is not used, NMI should be pulled high externally.
P6.0-
P6.7
82-89
I/O
5T
An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable
for input or output via direction bits. For a pin configured as
input, the output driver is put into high-impedance state. Port 6
outputs can be configured as push/pull or open drain drivers.
The following Port 6 pins have alternate functions:
82
O
5T
P6.0
CS0
Chip Select 0 Output
...
86
O
5T
P6.4
CS4
Chip Select 4 Output
87
I
5T
P6.5
HOLD
External Master Hold Request Input
(Master mode: O, Slave mode: I)
88
I/O
5T
P6.6
HLDA
Hold Acknowledge Output
89
O
5T
P6.7
BREQ
Bus Request Output
Sy
mb
o
l
Pi
n
N
u
mb
e
r
(T
Q
F
P
)
In
p
u
t(I
)
Ou
tp
ut
(
O
)
Ki
n
d
1)
Fu
nc
ti
on
Table 1 Pin definitions
1
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