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參數(shù)資料
| 型號： | SDC2200DUT3D |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | OPGA-453 |
| 文件頁數(shù)： | 98/102頁 |
| 文件大?。?/td> | 3049K |
| 代理商： | SDC2200DUT3D |
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31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
Appendix B - Conventions and Abbreviations
83
Appendix B
Conventions and
Abbreviations
This section contains information about the conventions and
abbreviations used in this document.
Signals and Bits
■
Active-Low Signals—Signal names containing a pound sign,
such as SFILL#, indicate active-Low signals. They are
asserted in their Low-voltage state and negated in their
High-voltage state. When used in this context, High and Low
are written with an initial upper case letter.
■
Signal Ranges—In a range of signals, the highest and lowest
signal numbers are contained in brackets and separated by a
colon (for example, D[63:0]).
■
Reserved Bits and Signals—Signals or bus bits marked
reserved must be driven inactive or left unconnected, as
indicated in the signal descriptions. These bits and signals
are reserved by AMD for future implementations. When
software reads registers with reserved bits, the reserved bits
must be masked. When software writes such registers, it
must
first
read
the
register
and
change
only
the
non-reserved bits before writing back to the register.
■
Three-State—In timing diagrams, signal ranges that are
high impedance are shown as a straight horizontal line
half-way between the high and low levels.
■
Invalid and Don’t-Care—In timing diagrams, signal ranges
that are invalid or don't-care are filled with a screen pattern.
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