參數(shù)資料
型號: SDC2200DUT3D
廠商: ADVANCED MICRO DEVICES INC
元件分類: 微控制器/微處理器
英文描述: 1500 MHz, MICROPROCESSOR, CPGA453
封裝: OPGA-453
文件頁數(shù): 84/102頁
文件大?。?/td> 3049K
代理商: SDC2200DUT3D
70
Pin Descriptions
Chapter 10
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
31994A—1August 2004
FID[3:0] Pins
FID[3] (Y3), FID[2] (Y1), FID[1] (W3), and FID[0] (W1) are the
4-bit processor clock-to-SYSCLK ratio.
Table 21 describes the encodings of the clock multipliers on
FID[3:0].
The FID[3:0] signals are open-drain processor outputs that are
pulled High on the motherboard and sampled by the chipset to
determine the SIP (serial initialization packet) that is sent to
the processor. The FID[3:0] signals are valid after PWROK is
asserted. The FID[3:0]signals must not be sampled until they
become valid. See the AMD Athlon and AMD Duron System
Bus Specification, order# 21902 for more information about
Serialization Initialization Packets and SIP protocol.
The processor FID[3:0] outputs are open-drain and 2.5-V
tolerant. To prevent damage to the processor, do not pull these
Table 21. FID[3:0] Clock Multiplier Encodings
FID[3:0]2
Processor Clock to SYSCLK Frequency Ratio
0000
11
0001
11.5
0010
12
0011
≥ 12.51
0100
5
0101
5.5
0110
6
0111
6.5
1000
7
1001
7.5
1010
8
1011
8.5
1100
9
1101
9.5
1110
10
1111
10.5
Notes:
1. All ratios greater than or equal to 12.5x have the same FID[3:0] code of 0011b, which causes
the SIP configuration for all ratios of 12.5x or greater to be the same.
2. BIOS initializes the CLK_Ctl MSR during the POST routine. This CLK_Ctl setting is used with all
FID combinations and selects a Halt disconnect divisor and a Stop Grant disconnect divisor.
For more information, refer to the AMD Athlon and AMD Duron Processors BIOS,
Software, and Debug Developers Guide, order# 21656.
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