參數(shù)資料
型號： SDC2200DUT3D
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 1500 MHz, MICROPROCESSOR, CPGA453
封裝： OPGA-453
文件頁數(shù)： 25/102頁
文件大小： 3049K
代理商： SDC2200DUT3D
Chapter 4
Power Management
17
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
Figure 7. Processor Connect State Diagram
Condition
1
CONNECT is deasserted by the Northbridge (for a
previously sent Halt or Stop Grant special cycle).
2
Processor receives a wake-up event and must cancel
the disconnect request.
3 Deassert PROCRDY and slow down internal clocks.
4
Processor wake-up event or CONNECT asserted by
Northbridge.
5 CLKFWDRST is deasserted by the Northbridge.
6
Forward clocks start three SYSCLK periods after
CLKFWDRST is deasserted.
Action
A CLKFWDRST is asserted by the Northbridge.
B Issue a Connect special cycle.*
C
Return internal clocks to full speed and assert
PROCRDY.
Note:
*
The Connect special cycle is only issued after a
processor wake-up event (interrupt or STPCLK#
deassertion) occurs. If the AMD Athlon system
bus is connected so the Northbridge can probe the
processor, a Connect special cycle is not issued at
that time (it is only issued after a subsequent
processor wake-up event).
Connect
Disconnect
Pending
Disconnect
Connect
Pending 1
Connect
Pending 2
1
3/A
4/C
5
6/B
2/B
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