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參數(shù)資料
| 型號： | SDC2200DUT3D |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1500 MHz, MICROPROCESSOR, CPGA453 |
| 封裝： | OPGA-453 |
| 文件頁數(shù)： | 52/102頁 |
| 文件大?。?/td> | 3049K |
| 代理商： | SDC2200DUT3D |
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Chapter 8
Signal and Power-Up Requirements
41
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
clock must be valid at this time. The system clocks are
designed to be running after 3.3 V has been within
specification for three milliseconds.
4. PWROK assertion to deassertion of RESET#
The duration of RESET# assertion during cold boots is
intended to satisfy the time it takes for the PLL to lock with
a less than 1 ns phase error. The processor PLL begins to
run after PWROK is asserted and the internal clock grid is
switched from the ring oscillator to the PLL. The PLL lock
time may take from hundreds of nanoseconds to tens of
microseconds. It is recommended that the minimum time
between PWROK assertion to the deassertion of RESET# be
at least 1.0 milliseconds. Southbridges enforce a delay of
1.5 to 2.0 milliseconds between PWRGD (Southbridge
version of PWROK) assertion and NB_RESET# deassertion.
5. PWROK
must
be
monotonic
and
meet
the
timing
requirements as defined in Table 12, “General AC and DC
Characteristics,” on page 32. The processor should not
switch between the ring oscillator and the PLL after the
initial assertion of PWROK.
6. NB_RESET# must be asserted (causing CONNECT to also
assert) before RESET# is deasserted. In practice all
Southbridges enforce this requirement.
If NB_RESET# does not assert until after RESET# has
deasserted, the processor misinterprets the CONNECT
assertion (due to NB_RESET# being asserted) as the
beginning of the SIP transfer. There must be sufficient
overlap in the resets to ensure that CONNECT is sampled
asserted by the processor before RESET# is deasserted.
7. The FID[3:0] signals are valid within 100 ns after PWROK is
asserted. The chipset must not sample the FID[3:0] signals
until they become valid.
Processor-Based Motherboard Design Guide, order# 24363, for
the
specific
implementation
and
additional
circuitry
required.
8. The FID[3:0] signals become valid within 100 ns after
RESET# is asserted. Refer to the AMD Athlon Processor-
Based Motherboard Design Guide, order# 24363, for the
specific implementation and additional circuitry required.
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