參數(shù)資料
型號(hào)： SDC2200DUT3D
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 1500 MHz, MICROPROCESSOR, CPGA453
封裝： OPGA-453
文件頁(yè)數(shù)： 23/102頁(yè)
文件大小： 3049K
代理商： SDC2200DUT3D
Chapter 4
Power Management
15
31994A—1August 2004
AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Athlon system bus, and puts the processor into the
Working state.
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The
Southbridge
deasserts
STPCLK#,
informing
the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded
clocks
between
the
processor
and
the
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
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