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參數(shù)資料
| 型號： | SCANPSC110FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大小： | 269K |
| 代理商： | SCANPSC110FSCX |
15
www.fairchildsemi.com
SCANPSC1
10F
Special Features
BIST SUPPORT
The sequence of instructions to run BIST testing on a
parked SCANPSC110F Bridge port is as follows:
1. Pre-load the Boundary register of the device under test
if needed.
2.
Initialize the TCK counter to 00000000 Hex. Note that
the TCK counter is initialized to 00000000 Hex upon
Test-Logic-Reset, so this step may not be necessary.
3. Issue the CNTRON instruction to the SCANPSC110F,
to enable the TCK counter.
4. Shift the PARKRTI instruction into the SCANPSC110F
instruction register and BIST instruction into the
instruction register of the device under test.
5. Issue the CNTRSEL instruction to the SCANPSC110F.
6. Load the TCK counter (Shift the 32-bit value represent-
ing the number of TCKL cycles needed to execute the
BIST operation into the TCK counter register).
7. Bit 7 of the Mode register can be scanned to check the
status of the TCK counter, (MODESEL instruction fol-
lowed by a Shift-DR). Bit 7 logic “0” means the counter
has not reached terminal count, logic “1” means that
the counter has reached terminal count and the BIST
operation has completed.
8. Execute the CNTROFF instruction.
9. Unpark the LSP and scan out the result of the BIST
operation (the CNTROFF instruction must be executed
before unparking the LSP).
The Self test will begin on the rising edge of TCKB following
the Update-DRTAP controller state.
RESET
Reset operations can be performed at three levels. The
highest level resets all SCANPSC110F registers and all of
the
local
scan
chains
of
selected
and
unselected
SCANPSC110Fs. This “Level 1” reset is performed when-
ever the SCANPSC110F TAP Controller enters the Test-
Logic-Reset state. Test-Logic-Reset can be entered syn-
chronously by forcing TMSB high for at least five (5) TCKB
pulses, or asynchronously by asserting the TRST pin. A
“Level 1” reset forces all SCANPSC110Fs into the Wait-
For-Address state, parks all local scan chains in the Test-
Logic-Reset state, and initializes all SCANPSC110F regis-
ters.
TABLE 10. Reset Configurations for Registers
The SOFTRESET instruction is provided to perform a
“Level 2” reset of all LSP's of selected SCANPSC110Fs.
SOFTRESET forces all TMSL signals HIGH, placing the
corresponding local TAP Controllers in the Test-Logic-
Reset state within five (5) TCKB cycles.
The third level of reset is the resetting of individual local
ports. An individual LSP can be reset by parking the port in
the Test-Logic-Reset state via the PARKTLR instruction. To
reset an individual LSP that is parked in one of the other
parked states, the LSP must first be unparked via the
UNPARK instruction.
PORT SYNCHRONIZATION
When a LSP is not being accessed, it is placed in one of
the four TAP Controller states: Test-Logic-Reset, Run-Test/
Idle, Pause-DR, or Pause-IR. The SCANPSC110F is able
to park a local chain by controlling the local Test Mode
Select outputs (TMSL(1–3)) (see Figure 4). TMSLn is forced
high for parking in the Test-Logic-Reset state, and forced
LOW for parking in Run-Test/Idle, Pause-IR, or Pause-DR
states. Local chain access is achieved by issuing the
UNPARK instruction. The LSPs do not become unparked
until the SCANPSC110F TAP Controller is sequenced
through a specified synchronization state. Synchronization
occurs in the Run-Test/Idle state for LSPs parked in Test-
Logic-Reset or Run-Test/Idle; and in the Pause-DR or
Pause-IR state for ports parked in Pause-DR or Pause-IR,
respectively.
Figures 11, 12 show the waveforms for synchronization of
a local chain that was parked in the Test-Logic-Reset state.
Once the UNPARK instruction is received in the instruction
register, the LSPC forces TMSL LOW on the falling edge of
TCKB.
FIGURE 11. Local Scan Port Synchronization on Second Pass
Register
Bit Width
Initial Hex Value
MCGR
2
0
Instruction
8
AA (IDCODE Instruction)
Mode
8
01
LFSR
16
0000
32-Bit Counter
32
00000000
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