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參數(shù)資料
| 型號： | SCANPSC110FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 25/25頁 |
| 文件大?。?/td> | 269K |
| 代理商： | SCANPSC110FSCX |
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www.fairchildsemi.com
SCANPSC1
10F
Level 1 Protocol
ADDRESSING MODES
The SCANPSC110F Bridge supports “single” and “multi-
ple” modes of addressing a SCANPSC110F. The “single”
mode will select one SCANPSC110F and is called Direct
Addressing. More than one SCANPSC110F device can be
selected via the Broadcast and Multi-Cast Addressing
modes.
TABLE 4. SCANPSC110F Bridge Address Modes
Note 2: Hex address ’7X’, ’BX’, or ’FX’ may be used instead of ’3X’.
Note 3: Only the six (6) LSB’s of the address is compared to the S(0–5) inputs. The two (2) MSB's are “don't cares”.
DIRECT ADDRESSING
The SCANPSC110F enters the Wait-For-Address state
when:
1. its TAP Controller enters the Test-Logic-Reset state, or
2. its instruction register is updated with the GOTOWAIT
instruction (while either selected or unselected).
Each SCANPSC110F within a scan network must be stati-
cally configured with a unique address via its S(0–5) inputs.
While the SCANPSC110F controller is in the Wait-For-
Address state, data shifted into bits 5 through 0 of the
instruction register is compared with the address present
on the S(0–5)inputs in the Update-IR state. If the six (6)
LSBs of the instruction register match the address on the
S(0–5) inputs, (see Figure 6) the SCANPSC110F becomes
selected, and is ready to receive Level 2 Protocol (i.e., fur-
ther instructions). When the SCANPSC110F is selected, its
device identification register is inserted into the active scan
chain.
All SCANPSC110Fs whose S(0–5) address does not match
the instruction register address become unselected. They
will remain unselected until either their TAP Controller
enters the Test-Logic-Reset state, or their instruction regis-
ter is updated with the GOTOWAIT instruction.
FIGURE 6. Direct Addressing: Device Address Loaded into Instruction Register
BROADCAST ADDRESSING
The Broadcast Address allows a tester to simultaneously
select all SCANPSC110Fs in a test network. This mode is
useful in testing systems which contain multiple identical
boards. To avoid bus contention between scan-path output
drivers on different boards, each SCANPSC110F’s TDOB
buffer is always 3-stated while in Broadcast mode. In this
configuration, the on-chip Linear Feedback Shift Register
(LFSR) can be used to accumulate a test result signature
for each board that can be read back later by direct-
addressing each board’s SCANPSC110F.
MULTI-CAST ADDRESSING
As a way to make the broadcast mechanism more selec-
tive, the SCANPSC110F provides a “Multi-cast” addressing
mode.
A
SCANPSC110F's
multi-cast
group
register
(MCGR)
can
be
programmed
to
assign
that
SCANPSC110F to one of four (4) Multi-Cast groups. When
SCANPSC110Fs
in
the
Wait-For-Address
state
are
updated with a Multi-Cast address, all SCANPSC110Fs
whose MCGR matches the Multi-Cast group will become
selected. As in Broadcast mode, TDOB is always 3-stated
while in Multi-cast mode.
Address Types
Hex Address
(Note 2)
Binary Address
(Note 3)
TDOB State
Direct Address
00 to 3A
XX000000 to XX111010
Normal IEEE Std. 1149.1
Broadcast Address
3B
XX111011
Always 3-STATED
Multi-Cast Group 0
3C
XX111100
Always 3-STATED
Multi-Cast Group 1
3D
XX111101
Always 3-STATED
Multi-Cast Group 2
3E
XX111110
Always 3-STATED
Multi-Cast Group 3
3F
XX111111
Always 3-STATED
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