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參數(shù)資料
| 型號： | SCANPSC110FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 269K |
| 代理商： | SCANPSC110FSCX |
www.fairchildsemi.com
14
SCAN
PSC1
10
F
Register Descriptions (Continued)
TABLE 7. Mode Register Control of LSPN
X
= don’t care
Register
= SCANPSC110F instruction register or any of the SCANPSC110F test data registers
PAD
= insertion of a 1-bit register for synchronization
Mode Register
The mode register is an 8-bit data register used primarily to
configure the Local Scan Port Network. The mode register
is initialized to “00000001” binary upon entering the Test-
Logic-Reset state.
Bits 0, 1, 2, and 4 are used for scan chain configuration as
described in Table 7. When the UNPARK instruction is exe-
cuted, the scan chain configuration will be as shown in
Table 7 above. When all LSPs are parked, the scan chain
configuration
will
be
TDIB→SCANPSC110F register→TDOB. Bit 3 is used for
TCKLn configuration, see Table 8.
TABLE 8. Test Clock Configuration
Bit 3 is normally set to logic “0” so that TCKL is free-running
when the local scan ports are parked. When the local ports
are parked, bit 3 can be programmed with logic “1”, forcing
all of the LSP TCKL's to stop. This feature can be used in
power sensitive applications to reduce the power con-
sumed by the test circuitry in parts of the system that are
not under test. Bit 3 of the mode register must be reset
to logic “0” before the UNPARK instruction is exe-
cuted.
Bit 7 is a status bit for the TCK counter. When the counter
is on and has reached terminal count (Zero) Bit 7 of the
mode register will be high (logic “1”). Bit 7 is read-only and
will be LOW in all other conditions.
Bits 5 and 6 are reserved for future use.
Device Identification Register
The device identification register (IDREG) is a 32-bit regis-
ter compliant with IEEE Std. 1149.1. When the IDCODE
instruction is active, the identification register is loaded with
the value “0FC0E01F” Hex upon leaving the Capture-DR
state (on the rising edge of the TCKB).
TABLE 9. Detailed Device Identification (Binary)
Linear Feedback Shift Register
The SCANPSC110F contains a “signature compactor”
which supports test result evaluation in a multi-chain envi-
ronment. The signature compactor consists of a 16-bit lin-
ear-feedback shift register (LFSR) which can monitor local-
port scan data as it is shifted “upstream” from the
SCANPSC110F's local-port network. Once the LFSR is
enabled, the LFSR's state changes in a reproducible way
as each local-port data bit is shifted in from the local-port
network. When all local-port data has been scanned in, the
LFSR contains a 16-bit signature value which can be com-
pared against a signature computed for the expected
results vector.
The LFSR uses the following feedback polynomial:
F (x)
= X16 + X12 + X3 + X + 1
This signature compactor is used to compress serial data
shifted in from the local scan chain, into a 16-bit signature.
This signature can then be shifted out for comparison with
an expected value. This allows users to test long scan
chains in parallel, via Broadcast or Multi-Cast addressing
modes, and check only the 16-bit signatures from each
module.
The LFSR is initialized with a value of “0000” Hex upon
reset.
32-Bit TCK Counter Register:
The 32-bit TCK counter register enables BIST testing that
requires “n” TCK cycles, to be run on a parked LSP while
another SCANPSC110F port is being tested. The CNTR-
SEL instruction can be used to load a count-down value
into the counter register via the active scan chain. When
the counter is enabled (via the CNTRON instruction), and
the LSP is parked, the local TCKs will stop and be held
LOW when terminal count is reached.
The TCK counter is initialized with a value of “00000000”
Hex upon reset.
Mode Register
Scan Chain Configuration (If unparked)
XXX0X000
TDIB→Register→TDOB
XXX0X001
TDIB→Register→LSP1→PAD→TDOB
XXX0X010
TDIB→Register→LSP2→PAD→TDOB
XXX0X011
TDIB→Register→LSP1→PAD→LSP2→PAD→TDOB
XXX0X100
TDIB→Register→LSP3→PAD→TDOB
XXX0X101
TDIB→Register→LSP1→PAD→LSP3→PAD→TDOB
XXX0X110
TDIB→Register→LSP2→PAD→LSP3→PAD→TDOB
XXX0X111
TDIB→Register→LSP1→PAD→LSP2→PAD→LSP3→PAD→TDOB
XXX1XXXX
TDIB→Register→TDOB (Loopback)
Bit 3
LSPn
TCKLn
1
Parked
Stop
0
Parked
Run
1
Unparked
Run
0
Unparked
Run
Bits
Bit
31–28
27–12
11–1
0
Version
Part Number
Manufacturer
1
Identity
0000
1111 1100 0000 1110
0000 0001 111
1
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