參數(shù)資料
型號(hào)： SCANPSC110FSCX
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類(lèi)： 微控制器/微處理器
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28
封裝： 0.300 INCH, MS-013, SOIC-28
文件頁(yè)數(shù)： 15/25頁(yè)
文件大?。?/td> 269K
代理商： SCANPSC110FSCX
www.fairchildsemi.com
22
SCAN
PSC1
10
F
Appendix
Note: The value of the TMS during the rising edge of TCK is located next to each transition.
FIGURE 17. IEEE 1149.1 TAP Controller State Diagram
Applications Example
FIGURE 18. Boundary Scan Backplane with 10 Card Slots, 8 Slots Are Filled with Boards
The following sequence gives an example of how one
might use the SCANPSC110F Bridge to perform 1149.1
operations via a multi-drop scan backplane. The system
involved has 10 card slots, 8 of which are filled with mod-
ules, and 2 slots are empty. (See Figure 18 ).
More Information can be found in Application Notes:
AN-1023
Structural System Test via IEEE Std. 1149.1
with SCANPSC110F Hierarchical and Multi-
drop Addressable JTAG Port
AN-1022
Boundary Scan, An Enabling Technology for
System Level Embedded Test
1. After the system is powered up a level-1 reset is per-
formed via the TRST input. All TAP Controllers (both
SCANPSC110F and local) are asynchronously forced
into the Test-Logic-Reset state. All LSP Controllers are
in the parked Test-Logic-Reset state; this forces the
TMSL outputs of each port to a logic “1”, keeping all
board TAPs in the Test-Logic-Reset state.
2. The first task of the tester is to find out which slots are
occupied on the backplane. This is accomplished by
performing a serial poll of each slot address in the sys-
tem,
as
assigned
by
the
S0–5 value of each
SCANPSC110F in the system.
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