
15
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SCANPSC100F
Serial Scan Interface (SSI) (Continued)
controllers within the scan chain(s) must be considered
when developing Loop-Back test vectors to prevent undes-
ired shifting of data or TAP controller transitions within the
scan chain.
32-BIT COUNTER (CNT32)
CNT32 is a 32-bit, count-down binary counter arranged in
four 8-bit segments. CNT32 can be loaded independent of
its enable/disable status. Loading requires four consecu-
tive writes to its address (least significant byte first). These
four writes must not be interleaved with writes to any other
address or the CNT32 write control logic will be re-initial-
ized. This re-initialization will result in a partially filled
counter with an undesired value. CNT32 is reset each time
the counter hits terminal count or by asserting the RST pin.
A synchronous reset condition (setting Mode2(1)) does not
reset the counter and a new value must be written to
CNT32 to provide the desired number of TCK cycles.
SINGLE STEP MODE: All four 8-bit registers are readable
for testability; however, there are no update latches similar
to the ones used for the status bits. To stabilize the counter
for read operations during on-board test, the Single Step
Mode has been added. This allows the user to place
CNT32 in any state and then count for one SCK cycle (TCK
will not toggle when in singled step mode). The result can
then be read from the PPI. The counter can be tested by
loading it with values at its boundary conditions, and then
clocking for one cycle to see the results. For example, the
counter could be loaded with the value:
00000001
00000000
The next step is to set the Single Step Mode bit so that the
counter counts down to the next state and stops. The next
value is:
00000000
11111111
Four read cycles using the PPI will reveal the results of the
test.
Note: CNT32 will not wrap from terminal count (i.e., 00000000h decre-
mented by 1 will remain unchanged and will not wrap to FFFFFFFFh).
Therefore, CNT32 should be loaded with a non-zero value prior to a Single
Step Mode Operation.
TIMING WAVEFORMS
FIGURE 15. Serial Scan Interface Timing
Embedded Test Software Support
A SCANPSC100 device driver is provided by Fairchild to
supply functions for performing write, read and shift opera-
tions. Fairchild also offers a suite of software tools (called
SCAN EASE) which enables ATPG or custom generated
test vectors to be embedded, applied and evaluated within
an IEEE 1149.1 compatible system. SCAN EASE is written
to run on a wide range of processor and memory architec-
tures. SCAN EASE includes the source code (ANSI C) and
is modular to allow user modification based on application
specific needs.