- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄192316 > SCANPSC100FSCX (FAIRCHILD SEMICONDUCTOR CORP) PDF資料下載
參數(shù)資料
| 型號： | SCANPSC100FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100FSCX |
3
www.fairchildsemi.com
SCANPSC100F
Chip Architecture
The SCANPSC100 is designed to act together with a paral-
lel bus host as a serial test bus master. Parallel data is writ-
ten by the host to the SCANPSC100, which serializes the
data for application to a serial test bus. Serial data return-
ing from the target scan chain(s) is placed on the processor
port for parallel reads. Several features are included in the
SCANPSC100 which make scan test communication more
convenient and efficient.
Figure 1 shows the major functional blocks of the
SCANPSC100 design. The Parallel Processor Interface
(PPI) is an asynchronous, 8-bit parallel interface which is
used by the host processor to write and read data. The PPI
generates the necessary internal data, address, and con-
trol signals to complete internal write and read operations.
The Serial Scan Interface (SSI) consists of a bank of dou-
ble-buffered parallel/serial shift registers (i.e., a 2 x 8 bit
FIFO), or Shifter/Buffers. The double buffering improves
efficiency by allowing parallel writes or reads to/from one of
the two 8-bit FIFOs within the shifter/buffer while the other
FIFO is shifting data to/from the scan chain. Three Shifter/
Buffers are provided for outgoing serial data and one for
incoming serial data. Test Data Out (TDO) is for scanning
out test data while the two Test Mode Select signals
(TMS0/1) are used to provide user specific control data.
Test Data In (TDI) receives serial data from the scan chain.
A local control block is associated with each Shifter/Buffer
to provide shift and load control as well as providing full or
empty status. The SSI also provides Test Clock (TCK) Con-
trol. TCK is stopped and started depending on the status of
the Shifter/Buffers or the 32-bit Counter. By stopping and
starting TCK, scan operations will proceed only when the
enabled Shifter/Buffers are ready to send and/or receive
serial data.
The 32-bit Counter (CNT32) is a count-down binary
counter included to assist in controlling the SSI. The initial
state of CNT32 is loaded from the parallel port with four
consecutive writes to its address. When enabled, CNT32 is
used to program the number of TCKs applied by the SSI to
the boundary scan chain(s). The value of CNT32 can also
be used to generate interrupts (i.e., when CNT32 reaches
terminal count) and to trigger SCANPSC100 features, such
as, Auto TMS High (discussed later within this datasheet).
The Mode and Status Registers are used to control and
observe the operation of the SSI and CNT32. Each of the
Shifter/Buffers and CNT32 have an associated mode bit
which enables it for participation in on-going operations.
Status bits can be used for polling operations.
FIGURE 1. SCANPSC100 Block Diagram
相關PDF資料 |
PDF描述 |
|---|---|
| SCANPSC110FSCX | |
| SCBA15FF | 5 A, SILICON, BRIDGE RECTIFIER DIODE |
| SCBC21WA4S0000G | 21 CONTACT(S), FEMALE, D SUBMINIATURE CONNECTOR, CRIMP |
| SCBM5W1M/F | 5-5 CONTACT(S), PANEL MOUNT, MALE-FEMALE, RECTANGULAR ADAPTER |
| SCBM5W5M/F | 5-5 CONTACT(S), PANEL MOUNT, MALE-FEMALE, RECTANGULAR ADAPTER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SCANPSC110 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110_ZFC3026B WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: |
| SCANPSC110F | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FDMQB | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:SCAN Bridge Hierarchical and Multidrop Addressable JTAG Port (IEEE1149.1 System Test Support) |
| SCANPSC110FDMQB WAF | 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。