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| 型號： | SCANPSC100FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100FSCX |
www.fairchildsemi.com
20
SCAN
PSC100
F
AC Electrical Characteristics/Operating Requirements (Continued)
Note 9: Voltage Range 5.0 is 5.0V
± 0.5V.
Note 10: SSC Mode
Symbol
Parameter
VCC
TA = +25°CTA = 40°C to +85°C
Units
Figure
(V)
CL = 50 pF
Number
(Note 9)
Min
Typ
Max
Min
Max
tW
Clock Pulse Width
SCK (L)
SCK (H)
5.0
19.5
12.0
19.5
ns
Figures 4, 6
18.5
14.0
18.5
tW1
Pulse Width
5.0
5.5
2.0
5.5
ns
Figures 4, 6
STB (H or L)
fMAX
Maximum
5.0
25
35
25
MHz
Frequency Clock
SERIAL SCAN INTERFACE (SSI)
tPD5
Prop Delay
5.0
3.0
8.0
11.0
3.0
12.0
ns
Figure 15
SCK to TCK
tPD6
Prop Delay
5.0
5.5
12.0
16.0
5.5
17.5
ns
Figure 15
SCK to TDO
tPD7
Prop Delay
5.0
4.5
11.0
14.5
4.5
15.5
ns
Figure 15
SCK to TMS
tPD8
Prop Delay
5.0
3.0
8.0
10.5
3.0
11.5
ns
Figure 15
FRZ to TCK
tEN4
Enable Time
5.0
2.0
7.0
10.0
2.0
11.0
ns
Figure 14
OE to JTAG
tDIS4
Disable Time
5.0
1.0
6.0
9.0
1.0
10.0
ns
Figure 14
OE to JTAG
tH5
Hold Time, H or L
5.0
0.5
1.5
0.5
ns
Figure 15
TDI to SCK (Note 10)
0.0
2.0
0.0
Figure 15
tS5
Setup Time, H or L
5.0
3.0
5.0
ns
Figure 15
TDI to SCK (Note 10)
6.5
3.5
6.5
Figure 15
RST RELATED TIMING
tPD
Prop Delay
5.0
8.0
17.5
24.0
8.0
25.5
ns
RST to D
tPD
Prop Delay
5.0
8.0
19.5
25.5
8.0
28.0
ns
RST to RDY
tPHL
Prop Delay
5.0
7.0
16.5
24.5
7.0
24.5
ns
RST to INT
tPLH
Prop Delay
5.0
5.5
12.5
17.0
5.5
18.5
ns
RST to TDO
tPLH
Prop Delay
5.0
5.5
12.0
16.0
5.5
17.5
ns
RST to TMS
tWR
Pulse Width
5.0
6.0
4.0
6.0
ns
RST (L)
tREC
Recovery Time
5.0
1.0
0.5
1.0
ns
SCK from RST
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