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參數(shù)資料
| 型號： | SCANPSC100FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 17/21頁 |
| 文件大?。?/td> | 208K |
| 代理商： | SCANPSC100FSCX |
5
www.fairchildsemi.com
SCANPSC100F
Mode and Status Registers (Continued)
MODE REGISTER 2 (MODE2)
Write:
Read:
This register contains both mode and status bits. Bits 4–7
are status bits only. Bit 3 is a status bit during read opera-
tions and a mode bit during write operations. Bits 0–2 are
mode bits only. Upon RST low, or a synchronous reset, the
value placed in MODE2 is 10111000 (Read mode). Latches
used to update status bits 3–7 retain their last state upon
RST and are in an “unknown” state after power-up. To ini-
tialize the latches to a known state, they need to be
updated using the Update Status bit (bit 2) or continuous
update bit (bit 3).
Bit 7:
Set high if the TDO shifter/buffer is not full,
i.e., one or both 8-bit TDO FIFOs are ready to
be written to.
Bit 6:
Set high if the TDI shifter/buffer is not empty,
i.e., one or both 8-bit TDI FIFOs are ready to
be read from.
Bit 5:
Set high if the 32-bit counter has not been
loaded, or has reached terminal count.
Bit 4:
Set high if the TMS0 shifter/buffer is not full,
i.e., one or both 8-bit TMS0 FIFOs are ready
to be written to.
Bit 3
(Read Cycle):
Set high if the TMS1 shifter/buffer is not full,
i.e., one or both 8-bit TMS1 FIFOs are ready
to be written to.
Bit 3
(Write Cycle):
If set, will cause all status bits to be continu-
ously updated.
Bit 2
(Read Cycle):
Shows the state of the Continuous Update bit
during read operations (Bit 3 during writes).
Bit 2
(Write Cycle):
If set, will cause a pulse to be issued internally
that will update all status bits. This bit will be
reset upon completion of the pulse. The state
of this bit is not readable. It is reset upon RST
low.
Bit 1:
If set, will cause a synchronous reset of all
functions except the parallel interface. The
value of this bit will return to zero when the
reset operation is complete.
Bit 0:
If set, will cause the 32-bit counter to count for
one SCK cycle (no TCK cycle will be gener-
ated). The value of this bit will return to zero
when the single step operation is complete.
PROGRAMMING RESTRICTIONS
Because certain mode bits enable shift operations for cer-
tain functions, these mode bits should not be changed
when shift operations are in progress. The alignment of all
registers during shift operations is controlled by a 3-bit
counter in the TCK control block. Enabling or disabling a
function in the middle of a shift operation may disrupt the
logic necessary to keep all shifter/buffers byte-aligned.
For example, if the TDO shifter/buffer (already loaded) is
enabled while the 3-bit counter value is 3, the shifter/buffer
will only shift out only five bits of the first byte loaded.
The following bits should not be changed when shift opera-
tions are in progress, i.e., when TCK is enabled (see sec-
tion on TCK Control).
MODE0(7:3)
MODE1(4:3)
MODE2(0)
Parallel Processor Interface (PPI)
ADDRESS ASSIGNMENT
The following table defines which register is selected for
access with the address lines, A(2:0).
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Not
Continuous
Update
Single
Used
Update
Status
Reset
Step
CNT32
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TDO
TDI
CNT32
TMS0
TMS1
Continuous
Single
Status
Update
Reset
Step
CNT32
A2
A1
A0
R/W
Function
0
TDO Shifter/Buffer
0
1
Counter Register 1
0
1
0
TDI Shifter/Buffer
0
1
TDI Shifter/Buffer
0
1
0
TMS0 Shifter/Buffer
0
1
0
1
Counter Register 2
0
1
0
TMS1 Shifter/Buffer
0
1
Counter Register 3
1
0
32-Bit Counter
1
0
1
Counter Register 0
101
0
MODE0
101
1
MODE0
110
0
MODE1
110
1
MODE1
111
0
MODE2
111
1
MODE2
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