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| 型號： | SCANPSC100FSCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 微控制器/微處理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封裝： | 0.300 INCH, MS-013, SOIC-28 |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 208K |
| 代理商： | SCANPSC100FSCX |
19
www.fairchildsemi.com
SCANPSC100F
DC Electrical Characteristics (Continued)
Note 8: This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
AC Electrical Characteristics/Operating Requirements
Symbol
Parameter
VCC
TA = +25°CTA = 40°C to +85°C
Units
Conditions
(V)
Typ
Guaranteed Limits
ICCMAX
Maximum Quiescent
5.5
768
840
A
TDI, OE LOW
Supply Current
ICCT
Maximum
5.5
0.6
1.50
mA
VIN = VCC 2.1V
ICC/Input
Float: TDI, OE
ICCTR
Maximum
VIN = VCC 2.1V
ICC/Input
5.5
0.65
1.65
mA
TDI and OE Only
Float Untested Pin
ICCD
Dynamic Power
mA/
VIH = VCC, VIL = 0,
Supply Current
5.5
1.70
2.30
MHz
VCC = Max, Outputs Open,
(Note 8)
FSCK = 25 MHz
Symbol
Parameter
VCC
TA = +25°CTA = 40°C to +85°C
Units
Figure
(V)
CL = 50 pF
Number
(Note 9)
Min
Typ
Max
Min
Max
PARALLEL PROCESSOR INTERFACE (PPI)
tPD1
Prop Delay
5.0
14.0
19.5
5.0
24.0
ns
Figures 2, 3,
4
R/W to RDY
tPD2
Prop Delay
5.0
14.0
19.5
5.0
24.0
ns
Figures 2, 3
A to RDY
tPD3
Prop Delay
5.0
14.0
19.5
5.0
24.0
ns
Figure 3
A to D
tPD4
Prop Delay
5.0
8.0
14.5
19.0
8.0
20.5
ns
Figures 2, 3,
4, 6
STB to RDY
tEN1
Enable Time
5.0
2.0
7.0
10.0
2.0
11.0
ns
Figures 2, 3
CE to RDY
tDIS1
Disable Time
5.0
1.0
5.5
8.0
1.0
9.0
ns
Figures 2, 3
CE to RDY
tEN2
Enable Time
5.0
3.0
9.5
13.5
3.0
14.5
ns
Figure 3
CE to D
tDIS2
Disable Time
5.0
2.5
7.5
11.0
2.5
12.0
ns
Figure 3
CE to D
tEN3
Enable Time
5.0
3.0
10.0
14.0
3.0
15.0
ns
Figure 3
R/W to D
tDIS3
Disable Time
5.0
3.0
8.5
12.5
3.0
13.5
ns
Figure 3
R/W to D
tH1
Hold Time,
5.0
0.5
0.0
0.5
ns
Figures 2, 3,
4, 6
R/W to STB
tS1
Setup Time
5.0
1.0
0.0
1.0
ns
Figures 2, 3,
4, 6
R/W to STB
tH2
Hold Time,
5.0
4.0
2.5
4.0
ns
Figures 2, 3
A to STB
↑
tS2
Setup Time,
5.0
4.0
1.5
4.0
ns
Figures 2, 3
A to STB
↑
tH3
Hold Time,
5.0
4.0
2.5
4.0
ns
Figure 2
D to STB
↑
tS3
Setup Time,
5.0
0.0
2.0
0.0
ns
Figure 2
D to STB
↑
tS4
Setup Time,
5.0
7.0
5.0
7.0
ns
Figures 4, 5,
6, 7
STB
↑ to SCK ↓
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