
AMD Geode SC1200/SC1201 Processor Data Book
71
Signal Definitions
Revision 7.1
3.4.6
ACCESS.bus Interface Signals
Signal Name
Ball No.
Type
Description
Mux
EBGA
TEPBGA
AB1C
AJ13
N31
I/O
ACCESS.bus 1 Serial Clock. This is the
serial clock for the interface.
Note:
If selected as AB1C function but not
used, tie AB1C high.
GPIO20+DOCCS#
AB1D
AL12
N30
I/O
ACCESS.bus 1 Serial Data. This is the bidi-
rectional serial data signal for the interface.
Note:
If AB1D function is selected but not
used, tie AB1D high.
GPIO1+IOCS1#
AB2C
AJ12
N29
I/O
ACCESS.bus 2 Serial Clock. This is the
serial clock for the interface.
Note:
If AB2C function is selected but not
used, tie AB2C high.
GPIO12
AB2D
AL11
M29
I/O
ACCESS.bus 2 Serial Data. This is the bidi-
rectional serial data signal for the interface.
Note:
If AB2D function is selected but not
used, tie AB2D high.
GPIO13
3.4.7
PCI Bus Interface Signals
Signal Name
BalL No.
Type
Description
Mux
EBGA
TEPBGA
PCICLK
E2
A7
I
PCI Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI
signals are sampled on the rising edge of
PCICLK, and all timing parameters are
defined with respect to this edge.
---
PCICLK0
D3
A4
O
PCI Clock Outputs. PCICLK0 and PCICLK1
provide clock drives for the system at 33
MHz. These clocks are asynchronous to PCI
signals. There is low skew between all out-
puts. One of these clock signals should be
connected to the PCICLK input. All PCI clock
users in the system (including PCICLK)
should receive the clock with as low a skew
as possible.
FPCI_MON (Strap)
PCICLK1
E4
D6
O
LPC_ROM (Strap)
AD[31:24]
See
See
I/O
Multiplexed Address and Data. A bus
transaction consists of an address phase in
the cycle in which FRAME# is asserted fol-
lowed by one or more data phases. During
the address phase, AD[31:0] contain a physi-
cal 32-bit address. For I/O, this is a byte
address. For configuration and memory, it is
a DWORD address. During data phases,
AD[7:0] contain the least significant byte
(LSB) and AD[31:24] contain the most signifi-
cant byte (MSB).
D[7:0]
AD[23:0]
A[23:0]