
1998 May 15
6
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
7
PINNING
SYMBOL
PINS
I/O
DESCRIPTION
PLCC68
QFP64
TRST
1
58
I
Test reset input not (active LOW), for boundary scan test;
notes 1, 2, 3 and 4.
Test clock input for boundary scan test; note 3.
Real time control output: contains information about actual system
clock frequency, subcarrier frequency and phase and PAL sequence.
I
2
C-bus slave address select input; 0
→
48H for write, 49H for read,
1
→
4AH for write, 4BH for read.
I
2
C-bus serial data input/output.
I
2
C-bus serial clock input/output.
Not connected.
Not connected.
Not connected.
Not connected.
Test data output for boundary scan test; note 3.
Test data input for boundary scan test; note 3.
Test mode select input for boundary scan test or scan test; note 3.
Ground for analog supply voltage channel 2.
Analog input 22.
Positive supply voltage (+5 V) for analog channel 2.
Analog input 21.
Ground for analog supply voltage channel 1.
Analog input 12.
Positive supply voltage (+5 V) for analog channel 1.
Analog input 11.
Substrate (connected to analog ground).
Analog test output; for testing the analog input channels.
Positive supply voltage (+5 V) for internal CGC.
Ground for internal CGC.
Vertical reference output signal (I
2
C-bit COMPO = 0) or inverse
composite blank signal (I
2
C-bit COMPO = 1) (enabled via I
2
C-bit
OEHV).
Positive digital supply voltage 5 (+5 V).
Digital ground for positive supply voltage 5.
Line-locked system clock output (27 MHz).
Line-locked clock
1
2
output (13.5 MHz).
Clock reference output: this is a clock qualifier signal distributed by
the CGC for a data rate of LLC2. Using CREF all interfaces on the
VPO-bus are able to generate a bus timing with identical phase.
If CCIR-656 format is selected (OFTS0 = 1 and OFTS1 = 1) an
inverse composite blank signal (pixel qualifier) is provided on this pin.
TCK
RTCO
2
3
59
60
I
O
IICSA
4
61
I
SDA
SCL
n.c.
n.c.
n.c.
n.c.
TDO
TDI
TMS
V
SSA2
AI22
V
DDA2
AI21
V
SSA1
AI12
V
DDA1
AI11
V
SSS
AOUT
V
DDA0
V
SSA0
VREF
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O
O
I
I
GND
I
P
I
GND
I
P
I
GND
O
P
GND
O
V
DD5
V
SS5
LLC
LLC2
CREF
27
28
29
30
31
18
19
20
21
22
P
GND
O
O
O