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參數(shù)資料
| 型號： | SAA7111 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Video Input Processor VIP |
| 中文描述： | 視頻輸入處理器貴賓 |
| 文件頁數(shù)： | 12/64頁 |
| 文件大?。?/td> | 433K |
| 代理商： | SAA7111 |
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1998 May 15
12
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
The burst processing block provides the feedback loop of
the chroma PLL and contains;
Burst gate accumulator
Colour identification and killer
Comparison nominal/actual burst amplitude
Loop filter chroma gain control
Loop filter chroma PLL
PAL sequence generation
Increment generation for DTO1 with divider to generate
stable subcarrier for non-standard signals.
The chroma comb filter block eliminates crosstalk between
the chrominance channels in accordance with the PAL
standard requirements. For NTSC colour standards the
chroma comb filter can be used to eliminate crosstalk from
luminance to chrominance (cross-colour) for vertical
structures. The comb filter can be switched off if desired.
The resulting signals are fed to the variable Y-delay
compensation, RGB matrix, dithering circuit and output
interface, which contains the VPO output formatter and the
output control logic (see Fig.7).
8.4
Luminance processing
The 8-bit luminance signal, a digital CVBS format or a
luminance format (S-VHS, HI8), is fed through a
switchable prefilter. High frequency components are
emphasized to compensate for loss. The following
chrominance trap filter (f
0
= 4.43 or 3.58 MHz centre
frequency selectable) eliminates most of the colour carrier
signal, therefore, it must be bypassed for S-video
(S-VHS, HI8) signals.
The high frequency components of the luminance signal
can be peaked (control for sharpness improvement via
I
2
C-bus) in two band-pass filters with selectable transfer
characteristic. This signal is then added to the original
(unpeaked) signal. A switchable amplifier achieves
common DC amplification, because the DC gains are
different in both chrominance trap modes. The improved
luminance signal is fed to the BCS control located in the
chrominance processing block (see Fig.8).
8.5
RGB matrix
Y, Cr and Cb-data are converted after interpolation into
RGB data in accordance with CCIR-601 recommendation.
The realized matrix equations consider the digital
quantization:
R = Y + 1.371 Cr
G = Y
0.336 Cb
0.698 Cr
B = Y + 1.732 Cb.
After dithering (noise shaping) the RGB data is fed to the
output interface within the VPO-bus output formatter.
8.6
VPO-bus (digital outputs)
The 16-bit VPO-bus transfers digital data from the output
interfaces to a feature box or a field memory, a digital
colour space converter (SAA7192 DCSC), a video
enhancement and digital-to-analog processor
(SAA7165 VEDA2) or a colour graphics board
(Targa-format) as a graphical user interface.
The output data formats are controlled via the I
2
C-bus bits
OFTS0, OFTS1 and RGB888. Timing for the data stream
formats, 411 YUV (12-bit), 422 YUV (16-bit),
565 RGB (16-bit) and 888 RGB (24-bit) with an LLC2 data
rate, is achieved by marking each second positive rising
edge of the clock LLC in conjunction with CREF (clock
reference) (except RGB 888, see special application in
Fig.27). The higher output signals VPO15 to VPO8 in the
YUV format perform the digital luminance signal.
The lower output signals VPO7 to VPO0 in the YUV format
are the bits of the multiplexed colour difference signals
(B
Y) and (R
Y). The arrangement of the RGB 565 and
RGB 888 data stream bits on the VPO-bus is given in
Table 5.
The data stream format 422 YUV (the 8 higher output
signals VPO15 to VPO8) in LLC data rate fulfils the
CCIR-656 standard with its own timing reference code at
the start and end of each video data block.
A pixel in the format tables is the time required to transfer
a full set of samples. In the event of a 4 : 2 : 2 format two
luminance samples are transmitted in comparison to one
(B
Y) and one (R
Y) sample within a pixel. The time
frames are controlled by the HREF signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7120H | Digital video encoder |
| SAA7152 | Digital Video Comb Filter DCF |
| SAA7184 | Digital Video Encoders DENC2-M6 |
| SAA7187 | Digital video encoder (DENC2-SQ)(數(shù)字視頻編碼器) |
| SAA7188A | Digital Video Encoder (DENC2-M)(數(shù)字視頻編碼器(DENC2-M)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7111A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Video Input Processor EVIP |
| SAA7111AH | 制造商:NXP Semiconductors 功能描述: 制造商:Philips Semiconductor 功能描述: 制造商:NXP Semiconductors 功能描述:TV/VIDEO SIGNAL PROCESSOR, 64 Pin, Plastic, QFP |
| SAA7111AH/V4,557 | 功能描述:視頻 IC ENHANCED VIDEO INPUT RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7111AHBG | 功能描述:視頻 IC ENHANCED VIDEO INPUT PROCESSOR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SAA7111AHZ | 制造商:NXP Semiconductors 功能描述: |
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