參數(shù)資料
型號(hào)： SAA7111
廠商： NXP Semiconductors N.V.
英文描述： Video Input Processor VIP
中文描述： 視頻輸入處理器貴賓
文件頁(yè)數(shù)： 11/64頁(yè)
文件大?。?/td> 433K
代理商： SAA7111
1998 May 15
11
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
8
FUNCTIONAL DESCRIPTION
8.1
Analog input processing
The SAA7111 offers four analog signal inputs, two analog
main channels with clamp circuit, analog amplifier,
anti-alias filter and video CMOS ADC (see Fig.6).
8.2
Analog control circuits
The anti-alias filters are adapted to the line-locked clock
frequency with help from a filter control. During the vertical
blanking, time gain and clamping control are frozen.
8.2.1
C
LAMPING
The clamp control circuit controls the correct clamping of
the analog input signals. The coupling capacitor is also
used to store and filter the clamping voltage. An internal
digital clamp comparator generates the information with
respect to clamp-up or clamp-down. The clamping levels
for the two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
8.2.2
G
AIN CONTROL
Signal (white) peak control limits the gain at signal
overshoots. The flow charts (see Figs 10 and 11) show
more details of the AGC. The influence of supply voltage
variation within the specified range is automatically
eliminated by clamp and automatic gain control.
The gain control circuit receives (via the I
2
C-bus) the static
gain levels for the two analog amplifiers or controls one of
these amplifiers automatically via a built-in automatic gain
Fig.4
Analog line with clamp (HCL) and gain
range (HSY).
handbook, halfpage
HCL
MGC661
HSY
analog line blanking
TV line
1
60
225
GAIN
CLAMP
control (AGC) as part of the Analog Input Control (AICO).
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, matched to the ADCs input voltage range.
The AGC active time is the sync bottom of the video signal.
8.3
Chrominance processing
The 8-bit chrominance signal is fed to the multiplication
inputs of a quadrature demodulator, where two subcarrier
signals from the local oscillator DTO1 are applied
(0 and 90
°
phase relationship to the demodulator axis).
The frequency is dependent on the present colour
standard. The output signals of the multipliers are
low-pass filtered (four programmable characteristics) to
achieve the desired bandwidth for the colour difference
signals.
The colour difference signals are fed to the
Brightness/Contrast/Saturation block (BCS), which
includes the following five functions;
1.
AGC (automatic gain control for chrominance)
2.
Chroma amplitude matching [different gain factors for
(R
Y) and (B
Y) to achieve CCIR-601 levels
Cr and Cb]
3.
Chroma saturation control
4.
Luminance contrast and brightness
5.
Limiting YUV to the values 1 (min.) and 254 (max.) to
fulfil CCIR-601 requirements.
Fig.5 Automatic gain range.
handbook, halfpage
analog input level
controlled
ADC input level
maximum
minimum
range 10 dB
0 dB
0 dB
MGC660
+
4 dB
6 dB
(1 V(p-p) 75
)
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