參數(shù)資料
型號: SAA7111
廠商: NXP Semiconductors N.V.
英文描述: Video Input Processor VIP
中文描述: 視頻輸入處理器貴賓
文件頁數(shù): 30/64頁
文件大?。?/td> 433K
代理商: SAA7111
1998 May 15
30
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
Table 2
Digital output control
Notes
1.
2.
OFTS(1 : 0) = 10 or 01 or 00.
OFTS(1 : 0) = 11.
13 CLOCK SYSTEM
13.1
Clock generation circuit
The internal CGC generates the system clocks LLC, LLC2
and the clock reference signal CREF. The internal
generated LFCO (triangular waveform) is multiplied by
2 or 4 via the analog PLL (including phase detector, loop
filter, VCO and frequency divider). The rectangular output
signals have a 50% duty factor.
OEYC
FEI
VPO
15 to 0
(1)
15 to 8
(2)
7 to 0
(2)
0
1
0
1
0
0
1
1
Z
Z
Z
Z
Z
Z
active
Z
Z
active
Z
active
Table 3
Clock frequencies
CLOCK
FREQUENCY (MHz)
XTAL
LLC
LLC2
LLC4
LLC8
24.576
27
13.5
6.75
3.375
Fig.22 Block diagram of clock generation circuit.
handbook, full pagewidth
BAND PASS
FC = LLC/4
ZERO
CROSS
DETECTION
PHASE
DETECTION
LOOP
FILTER
DIVIDER
1/2
DIVIDER
1/2
OSCILLATOR
DELAY
CREF
MGC632
LLC2
LLC
LFCO
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