參數(shù)資料
型號: SAA7111
廠商: NXP Semiconductors N.V.
英文描述: Video Input Processor VIP
中文描述: 視頻輸入處理器貴賓
文件頁數(shù): 36/64頁
文件大?。?/td> 433K
代理商: SAA7111
1998 May 15
36
Philips Semiconductors
Product specification
Video Input Processor (VIP)
SAA7111
16 I
2
C-BUS DESCRIPTION
16.1
I
2
C-bus format
Table 6
Write procedure
Table 7
Read procedure (combined format)
Table 8
Description of I
2
C-bus format
Notes
1.
2.
If more than one byte DATA is transmitted then the auto-increment of the subaddress is performed.
During slave transmitter mode the SCL-LOW period may be extended by pulling SCL to LOW (in accordance with
the I
2
C-bus specification).
The I
2
C-bus subaddress 00 has to be initialized with 0 before being read.
3.
S
SLAVE ADDRESS W
ACK(s)
SUBADDRESS
ACK(s)
DATA (N BYTES)
ACK(s)
P
S
Sr
SLAVE ADDRESS W
SLAVE ADDRESS R
ACK(s)
ACK(s)
SUBADDRESS
DATA (N BYTES)
ACK(s)
ACK(m)
P
CODE
DESCRIPTION
S
Sr
Slave address W
Slave address R
ACK(s)
ACK(m)
Subaddress
Data
P
X = LSB slave
address
Slave address
START condition
repeated START condition
0100 1000b (IICSA = LOW) or 0100 1010b (IICSA = HIGH)
0100 1001b (IICSA = LOW) or 0100 1011b (IICSA = HIGH)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see Table 9
data byte, see; note 1 and Table 9
STOP condition
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
read = 49H or 4BH; note 2
write = 48H or 4AH
IICSA = 0 or 1
00H chip version
01H reserved
02H to 05H front-end part
06H to 12H decoder part
13H to 19H reserved
1AH to 1CH Line-21 text slicer part
1DH to 1EH reserved
1FH status byte
Subaddress
read and write; note 3
read and write
read and write
read only
read only
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