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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 6/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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MAILBOX OVERVIEW
S5933
MAILBOX OVERVIEW
The S5933 has eight 32-bit mailbox registers. The mail-
boxes are useful for passing command and status infor-
mation between the Add-On and the PCI bus. The PCI
interface has four incoming mailboxes (Add-On to PCI)
and four outgoing mailboxes (PCI to Add-On). The Add-
On interface has four incoming mailboxes (PCI to Add-
On) and four outgoing mailboxes (Add-On to PCI). The
PCI incoming and Add-On outgoing mailboxes are the
same, internally. The Add-On incoming and PCI outgo-
ing mailboxes are also the same, internally.
The mailbox status may be monitored in two ways.
The PCI and Add-On interfaces each have a mailbox
status register to indicate the empty/full status of
bytes within the mailboxes. The mailboxes may also
be configured to generate interrupts to the PCI and/or
Add-On interface. One outgoing and one incoming
mailbox on each interface can be configured to gen-
erate interrupts.
FUNCTIONAL DESCRIPTION
Figure 1 shows a block diagram of the PCI to Add-On
mailbox registers. Add-On incoming mailbox read ac-
cesses pass through an output interlock latch. This
prevents a PCI bus write to a PCI outgoing mailbox
from corrupting data being read by the Add-On. Fig-
ure 2 shows a block diagram of the Add-On to PCI
mailbox registers. PCI incoming mailbox reads also
pass through an interlocking mechanism. This pre-
vents an Add-On write to an outgoing mailbox from
corrupting data being read by the PCI bus. The fol-
lowing sections describe the mailbox flag functionality
and the mailbox interrupt capabilities.
MAILBOX
REGISTER
ADD-ON
BUS
"INCOMING
MAILBOX"
SELECT
OUTPUT
INTERLOCK
LATCH
OUTPUT
DRIVER
ADD-ON
BUS
MAILBOX
FULL
S
Q
D
"O"
LOAD ENABLE
READ ENABLE
EN
ADD-ON
RD#
SELECT#
EMPTY/FULL FF
Q
D
Q
D
PCI BUS
"OUTGOING MAILBOX"
SELECTED READ ENABLE
PCI
BUS
INTERFACE
ADD-ON
INTERFACE
"INCOMING MAILBOX"
Figure 1. Block Diagram - PCI to Add-On Mailbox Register
Figure 2. Block Diagram - Add-On to PCI Mailbox Register
MAILBOX
REGISTER
PCI
"INCOMING
MAILBOX"
SELECT
OUTPUT
INTERLOCK
LATCH
ADD-ON
BUS
"OUTGOING
MAILBOX"
WR#
SELECT#
PCI BUS
"INCOMING MAILBOX"
REGISTER
DECODE OF
ADR[6:2]
BE[3:0]#
MAILBOX
FULL
"O"
PCI READ PULSE
EMPTY/FULL FF
ADD-ON WRITE PULSE
SELECTED
READ PULSE
EN
Q
S
D
QD
PCI
BUS
INTERFACE
ADD-ON
INTERFACE
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相關(guān)代理商/技術(shù)參數(shù) |
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