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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 165/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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3-101
PCI BUS INTERFACE
S5933
PCI BUS MASTERSHIP
When the S5933 requires PCI bus mastership, it pre-
sents a request via the REQ# signal. This signal is
connected to the system’s PCI bus arbiter.
Only one initiator (bus master) may control the PCI
bus at a given time. The bus arbiter determines
which initiator is given control of the bus. Control is
granted to a requesting device by the arbiter assert-
ing that device’s grant signal (GNT#). Each REQ#/
GNT# signal pair is unique to a given PCI agent.
After asserting REQ#, the S5933 assumes bus own-
ership on the first PCI clock edge where its GNT#
input is asserted along with FRAME# and IRDY#
deasserted (indicating no other device is generating
PCI bus cycles). Once ownership is established by
the S5933, it maintains ownership as long as the
arbiter keeps its GNT# asserted. If GNT# is
deasserted, the S5933 completes the current trans-
action. The S5933 does this by deasserting FRAME#
and then deasserting IRDY# upon data transfer. Fig-
ure 13 shows a sequence where the S5933 is
granted ownership of the bus and then is preempted
by another master before the S5933 can finish its
current transaction.
Bus Mastership Latency Components
It is often necessary for system designers to predict
and guarantee that a minimum data transfer rate is
sustainable to support a particular application. In the
design of a bus mastering application, knowledge of
the maximum delay a device might encounter from
the time it requests the PCI bus to the time in which it
is actually granted the bus is desirable. This allows
the design to provide adequate data buffering. The
PCI specification refers to this bus request to grant
delay as “arbitration latency.”
Once a PCI initiator has been granted the bus, the
PCI specification defines the delay from the grant to
the new initiator’s assertion of FRAME# as the “bus
acquisition latency.” Afterwards, the delay from
FRAME# asserted to target ready (TRDY#) asserted
is defined as “target latency.” Figure 14 shows a
time-line depicting the components of PCI bus ac-
cess latency.
There are numerous configuration variations possible
with the PCI specification. A system designer can
determine whether a bus master can support a criti-
cal, timely transfer by establishing a specific configu-
ration and by defining these latency values. The
S5933, as an initiator, produces the fastest response
allowable for its bus acquisition latency (GNT# to
FRAME# asserted). The S5933 also implements the
PCI Master Latency Timer. Once granted the bus,
the S5933 is guaranteed ownership for a minimum
amount of time defined by the Master Latency Timer.
The S5933, as an initiator, cannot control the respon-
siveness of a particular target nor the bus arbitration
delay.
The PCI specification provides two mechanisms to
control the amount of time a master may own the
bus. One mechanism is through the master (master-
initiated termination). The other is by the target and is
achieved through a target-initiated disconnect.
Bus Arbitration
Although the PCI specification defines the condition
that constitutes bus ownership, it does not provide
rules to be used by the system’s PCI bus arbiter in
deciding which master is to be granted the PCI bus
next. The arbitration priority scheme implemented by
a system may be fixed, rotational, or custom. The
arbitration latency is a function of the system, not the
S5933.
Figure 14. PCI Bus Access Latency Components
Bus Access Latency
REQ#
Asserted
GNT#
Asserted
FRAME#
Asserted
TRDY#
Asserted
--Arbitration Latency--
--Bus Acquisition--
Latency
--Target Latency--
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