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參數(shù)資料
| 型號(hào)： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 158/176頁(yè) |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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3-94
PCI BUS INTERFACE
S5933
PCI Write Transfers
Write transfers on the PCI bus are one clock period
shorter than read transfers. This is because the
AD[31:0] bus does not require a turn-around cycle
between the address and data phases. When the
S5933 is accessed (target), it responds to a PCI bus
memory or I/O transfers. As a PCI initiator, the S5933
controller can also execute PCI memory write opera-
tions.
The timing diagram in Figure 4 represents an S5933
initiator PCI write operation transferring to a fast,
zero-wait-state memory target. The signals driven by
the S5933 during the transfer are FRAME#,
AD[31:0], C/BE[3:0]#, and IRDY#. The signals driven
by the target are DEVSEL# and TRDY#. As with PCI
reads, targets assert DEVSEL# and TRDY# after the
clock defining the end of the address phase (bound-
ary of clock periods 1 and 2 of Figure 4). TRDY# is
not driven until the target has accepted the data for the
PCI write. When the S5933 becomes the PCI initiator,
it attempts sustained zero-wait state burst writes until
one of the following occurs:
The memory target aborts the transfer
PCI bus grant (GNT# is removed)
The Add-On to PCI FIFO becomes empty
A higher priority (PCI to Add-On) S5933
transfer is pending (if programmed for priority)
The write transfer byte count reaches zero
Bus mastering is disabled from the Add-On
interface
Write accesses to the S5933 operation registers
(S5933 as a target) are shown in Figure 5. Here, the
S5933 asserts the signal STOP# in clock period 3.
STOP# is asserted because the S5933 supports fast,
zero-wait-state write cycles but does not support
burst writes to operation registers. Wait states may
be added by the initiator by not asserting the signal
IRDY# during clock 2 and beyond. There is only one
condition where writes to S5933 operation registers
do not return TRDY# (but do assert STOP#). This is
called a target-initiated termination or target discon-
nect and occurs when a write attempt is made to a
full S5933 FIFO. As with the read transfers, the as-
sertion of STOP# without the assertion of TRDY#
indicates the initiator should retry the operation later.
PCI CLOCK
FRAME #
AD [31:0]
C/BE [3:0]#
IRDY#
TRDY#
DEVSEL#
ADDRESS
DATA 1
BYTE EN 1
1
2
3
45
(I)
(T)
(I)
BYTE EN 3
BYTE EN 2
DATA 2
DATA 3
* BUS COMMAND = MEMORY WRITE
DATA
TRANSFER
#1
DATA
TRANSFER
#2
DATA
TRANSFER
#3
6
BUS COMMAND*
(I) = DRIVEN BY INITIATOR
(T) = DRIVEN BY TARGET
Figure 4. Zero Wait State Burst Write PCI Bus Transfer (S5933 as Initiator)
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相關(guān)代理商/技術(shù)參數(shù) |
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| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
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