參數(shù)資料
型號: S5933QE
廠商: APPLIEDMICRO INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PQFP160
封裝: PLASTIC, QFP-160
文件頁數(shù): 20/176頁
文件大?。?/td> 823K
代理商: S5933QE
3-129
FIFO OVERVIEW
S5933
Figure 3. PCI Read from a Full S5933 FIFO
PCI_CLK
PCI Signals
Add-on Signals
FRAME#
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
WRFULL
FWE
ADDR
DATA
Figure 4. PCI Read from an Empty S5933 FIFO (Target Disconnect)
PCI_CLK
PCI Signals
Add-on Signals
FRAME#
AD[31:0]
IRDY#
TRDY#
DEVSEL#
STOP#
WRFULL
FWE
ADDR
DATA
Target Disconnect with Retry
FIFO PCI Interface (Initiator Mode)
The S5933 can act as an initiator on the PCI bus.
This allows the device to gain control of the PCI bus
to transfer data to or from the FIFO. Internal address
and transfer count registers control the number of
PCI transfers and the locations of the transfers. The
following paragraphs assume the proper registers
and bits are programmed to enable bus mastering .
PCI read and write transfers from the S5933 are very
similar. The FIFO management scheme determines
when the S5933 asserts its PCI bus request (REQ#).
When bus grant (GNT#) is returned, the device be-
gins running PCI cycles. Once the S5933 controls the
bus, the FIFO management scheme is not important.
It only determines when PCI bus control is initially
requested. PCI bus reads and writes are always per-
formed as bursts by the S5933, if possible.
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