- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98071 > S5933QE (APPLIEDMICRO INC) PCI BUS CONTROLLER, PQFP160 PDF資料下載
參數(shù)資料
| 型號： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 139/176頁 |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁當(dāng)前第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁
3-75
ADD-ON BUS OPERATION REGISTERS
S5933
Table 3. Interrupt Control/Status Register
31:24
Reserved. Always zero.
23
Interrupt asserted. This read-only status bit indicates that one or more interrupt conditions is
present. This bit is nothing more than the ORing of the interrupt conditions described by bits, 20,
17 and 16 of this register.
22
Reserved. Always zero.
21
Master/Target Abort. This bit signifies that an interrupt has been generated due to the S5933
encountering a Master or Target abort during an S5933 initiated PCI bus cycle. This bit operates
as read or write one clear. Writing a one to this bit causes it to be cleared. Writing a zero to this
bit does nothing.
20
BIST. Built-In Self-Test interrupt. This interrupt occurs when a self test is initiated by the PCI
interface writing of the BIST configuration register. This bit will stay set until cleared by writing a
one to this location. Self test completion codes may be passed to the PCI BIST register by writing
to the AGCSTS register.
19
Read Transfer Complete. This bit signifies that an interrupt has been generated due to the
completion of a PCI bus master operation involving the transfer of data from the PCI bus to the
Add-On. This interrupt will occur when the Master Read Transfer Count register reaches zero.
This bit operates as read or write one clear. A write to this bit with the data of one will cause this
bit to be reset; a write to this bit with the data of zero will not change the state of this bit.
18
Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion
of a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. This
interrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates as
read or write one clear. A write to this bit with the data of one will cause this bit to be reset; a write to
this bit with the data of zero will not change the state of this bit.
17
Outgoing Mailbox Interrupt. This bit sets when the mailbox selected by bits 12 through 8 of this
register is read by the PCI interface. This bit operates as read or write one clear. A write to this bit
with the data as one will cause this bit to be reset; a write to this bit with the data as zero will not
change the state of this bit.
16
Incoming Mailbox Interrupt. This bit sets when the mailbox selected by bits 5 through 0 of this
register are written by the PCI interface. This bit operates as read or write one clear. A write to
this bit with the data of one will cause this bit to be reset; a write to this bit with the data as zero
will not change the state of this bit.
15
Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the
read transfer count reaches zero. This bit is read/write.
14
Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write
transfer count reaches zero. This bit is read/write.
13
Reserved. Always zero.
12
Enable outgoing mailbox interrupt. This bit allows a read by the PCI of the outgoing mailbox register
identified by bits 11 through 8 to produce an Add-On interface interrupt. This bit is read/write.
11:10
Outgoing Mailbox Interrupt Select. This field selects which of the four outgoing mailboxes is to be
the source for causing an outgoing mailbox interrupt. [00]b selects mailbox 1, [01]b selects
mailbox 2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.
9:8
Outgoing Mailbox Byte Interrupt select. This field selects which byte of the mailbox selected by
bits 11 and 10 above is to actually cause the interrupt. [00]b selects byte 0, [01]b selects byte 1,
[10]b selects byte 2, and [11]b selects byte 3. This field is read/write.
7:5
Reserved. Always zero.
Bit
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S6A0032 | 16 X 80 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC138 |
| S6A0069 | 16 X 40 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC80 |
| S6A0078 | 34 X 120 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC183 |
| S80296SA40 | 16-BIT, 40 MHz, MICROCONTROLLER, PQFP100 |
| S80486-DX4-75-S-V-8-B | 32-BIT, 75 MHz, MICROPROCESSOR, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935_07 | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S59355QRC | 制造商:AppliedMicro 功能描述: |
| S5935QF | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S5935QRC | 制造商:AppliedMicro 功能描述:PCI Master Device 160-Pin PQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。