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參數(shù)資料
| 型號： | S5933QE |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 125/176頁 |
| 文件大?。?/td> | 823K |
| 代理商： | S5933QE |
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3-61
PCI BUS OPERATION REGISTERS
S5933
Table 3. Interrupt Control/Status Register
Bit
Description
31:24
FIFO and Endian Control.
23
Interrupt asserted. This read only status bit indicates that one or more of the four possible interrupt
conditions is present. This bit is nothing more than the ORing of the interrupt conditions described
by bits 19 through 16 of this register.
22
Reserved. Always zero.
21
Target Abort. This bit signifies that an interrupt has been generated due to the S5933 encountering
a target abort during a PCI bus cycle while the S5933 was the current bus master. This bit operates
as read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset, a write
to this bit with the data of “zero” will not change the state of this bit.
20
Master Abort. This bit signifies that an interrupt has been generated due to the S5933 encountering
a Master Abort on the PCI bus. A master abort occurs when there is no target response to a PCI bus
cycle. This bit operates as read or write one clear. A write to this bit with the data of “one” will cause
this bit be reset, a write to this bit with the data of “zero” will not change the state of this bit.
19
Read Transfer Complete. This bit signifies that an interrupt has been generated due to the completion
of a PCI bus master operation involving the transfer of data from the PCI bus to the Add-On. This
interrupt will occur when the Master Read Transfer Count register reaches zero. This bit operates as
read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a write
to this bit with the data of “zero” will not change the state of this bit.
18
Write Transfer Complete. This bit signifies that an interrupt has been generated due to the completion
of a PCI bus master operation involving the transfer of data to the PCI bus from the Add-On. This
interrupt will occur when the Master Write Transfer Count register reaches zero. This bit operates as
read or write one clear. A write to this bit with the data of “one” will cause this bit to be reset; a write
to this bit with the data of “zero” will not change the state of this bit.
17
Incoming Mailbox Interrupt. This bit is set when the mailbox selected by bits 12 through 8 of this
register are written by the Add-On interface. This bit operates as read or write one clear. A write to
this bit with the data of “one” will cause this bit to be reset; a write to this bit with the data as “zero”
will not change the state of this bit.
16
Outgoing Mailbox Interrupt. This bit is set when the mailbox selected by bits 4 through 0 of this register
is read by the Add-On interface. This bit operates as read or write one clear. A write to this bit with
the data of “one” will cause this bit to be reset; a write to this bit with the data of “zero” will not change
the state of this bit.
15
Interrupt on Read Transfer Complete. This bit enables the occurrence of an interrupt when the read
transfer count reaches zero. This bit is read/write.
14
Interrupt on Write Transfer Complete. This bit enables the occurrence of an interrupt when the write
transfer count reaches zero. This bit is read/write.
13
Reserved. Always zero.
12
Enable incoming mailbox interrupt. This bit allows a write from the incoming mailbox register identified
by bits 11 through 8 to produce a PCI interface interrupt. This bit is read/write.
11:10
Incoming Mailbox Interrupt Select. This field selects which of the four incoming mailboxes is to be
the source for causing an incoming mailbox interrupt. [00]b selects mailbox 1, [01]b selects mailbox
2, [10]b selects mailbox 3 and [11]b selects mailbox 4. This field is read/write.
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