參數(shù)資料
型號(hào)： S29PL032J65BFI150
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝： 7 X 9 MM, LEAD FREE, FBGA-56
文件頁(yè)數(shù)： 66/94頁(yè)
文件大?。?/td> 949K
代理商： S29PL032J65BFI150
July 29, 2005 S29PL-J_00_A8
S29PL-J
67
Advance
Information
DQ2 toggles when the system reads at addresses within those sectors that have been selected
for erasure. (The system may use either OE# or CE# (CE1# / CE2# for PL129J) to control the
read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase
Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits
are required for sector and mode information. Refer to Table 23 to compare outputs for DQ2 and
DQ6.
Figure 12 shows the toggle bit algorithm in flowchart form, and the DQ2: Toggle Bit II explains
the algorithm. See also the DQ6: Toggle Bit I. Figure 24 shows the toggle bit timing diagram.
Figure 25 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 12 for the following discussion. Whenever the system initially begins reading tog-
gle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit
is toggling. Typically, the system would note and store the value of the toggle bit after the first
read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still tog-
gling, the system also should note whether the value of DQ5 is high (see the section on DQ5).
If it is, the system should then determine again whether the toggle bit is toggling, since the tog-
gle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling,
the device has successfully completed the program or erase operation. If it is still toggling, the
device did not completed the operation successfully, and the system must write the reset com-
mand to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and
DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through
successive read cycles, determining the status as described in the previous paragraph. Alterna-
tively, it may choose to perform other system tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine the status of the operation (top of Figure
12).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count
limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was
not successfully completed.
The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was
previously programmed to “0.” Only an erase operation can change a “0” back to a “1.”
Under this condition, the device halts the operation, and when the timing limit has been ex-
ceeded, DQ5 produces a “1.”
Under both these conditions, the system must write the reset command to return to the read
mode (or to the erase-suspend-read mode if a bank was previously in the erase-suspend-pro-
gram mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether
or not erasure has begun. (The sector erase timer does not apply to the chip erase command.)
If additional sectors are selected for erasure, the entire time-out also applies after each addi-
tional sector erase command. When the time-out period is complete, DQ3 switches from a “0”
to a “1.” See also the Sector Erase Command Sequence.
相關(guān)PDF資料
PDF描述
S29PL127J70BFI000 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
S29XS064R0PBHW010 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
S2C3R-1-12-H 4000 MHz - 12000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2 dB INSERTION LOSS
S2C5R-1-12-RC 4000 MHz - 18000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2.8 dB INSERTION LOSS
S2H3R-1H 10 MHz - 1000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.2 dB INSERTION LOSS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL032J70BAI120 功能描述:閃存 32Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BAI122 功能描述:閃存 32MB 閃存 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BAW120 功能描述:閃存 32MB 閃存 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BFI120 功能描述:閃存 32Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BFI120(E) 制造商:Spansion 功能描述:Cut Tape
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*