參數(shù)資料
型號(hào): S29PL032J65BFI150
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù): 57/94頁
文件大小: 949K
代理商: S29PL032J65BFI150
58
S29PL-J
S29PL-J_00_A8 July 29, 2005
Ad van c e
Inf o rmation
Note: See Table 21 for program command sequence.
Figure 9 Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing
two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then
followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The
device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any controls or timings during these op-
erations. Table 21 shows the address and data requirements for the chip erase command
sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and ad-
dresses are no longer latched. The system can determine the status of the erase operation by
using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information
on these status bits.
Any commands written during the chip erase operation are ignored. Note that Secured Silicon
Sector, autoselect, and CFI functions are unavailable when a [program/erase] operation is in
progress. However, note that a hardware reset immediately terminates the erase operation. If
that occurs, the chip erase command sequence should be reinitiated once that bank has returned
to reading array data, to ensure data integrity.
10 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables
in the AC Characteristics section for parameters, and Figure 21 section for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data?
No
Yes
Last Address?
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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