參數(shù)資料
型號: S29PL032J65BFI150
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù): 34/94頁
文件大?。?/td> 949K
代理商: S29PL032J65BFI150
2S29PL-J
S29PL-J_00_A8 July 29, 2005
Ad van c e
Inf o rmation
General Description
The PL127J/PL129J/PL064J/PL032J is a 128/128/64/32 Mbit, 3.0 volt-only Page Mode and Si-
multaneous Read/Write Flash memory device organized as 8/8/4/2 Mwords. The devices are
offered in the following packages:
11 mm x 8 mm, 80-ball Fine-pitch BGA standalone (PL127J)
8 mm x 11.6 mm, 64-ball Fine-pitch BGA multi-chip compatible (PL127J)
8.15 mm x 6.15 mm, 48-ball Fine-pitch BGA standalone (PL064J/PL032J)
7 mm x 9 mm, 56-ball Fine-pitch BGA multi-chip compatible (PL064J and PL032J)
20 mm x 14 mm, 56-pin TSOP (PL127J)
The word-wide data (x16) appears on DQ15-DQ0. This device can be programmed in-system or
in standard EPROM programmers. A 12.0 V VPP is not required for write or erase operations.
The device offers fast page access times of 20 to 30 ns, with corresponding random access times
of 55 to 70 ns, respectively, allowing high speed microprocessors to operate without wait states.
To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and
output enable (OE#) controls. Note: Device PL129J has 2 chip enable inputs (CE1#, CE2#).
Simultaneous Read/Write Operation with Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the
memory space into 4 banks, which can be considered to be four separate memory arrays as far
as certain operations are concerned. The device can improve overall system performance by al-
lowing a host system to program or erase in one bank, then immediately and simultaneously
read from another bank with zero latency (with two simultaneous operations operating at any
one time). This releases the system from waiting for the completion of a program or erase op-
eration, greatly improving system performance.
The device can be organized in both top and bottom sector configurations. The banks are orga-
nized as follows:
Page Mode Features
The page size is 8 words. After initial page access is accomplished, the page mode operation pro-
vides fast read access speed of random locations within that page.
Standard Flash Memory Features
The device requires a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write
functions. Internally generated and regulated voltages are provided for the program and erase
operations.
The device is entirely command set compatible with the JEDEC 42.4 single-power-supply
Flash standard. Commands are written to the command register using standard microproces-
sor write timing. Register contents serve as inputs to an internal state-machine that controls the
Bank
PL127J Sectors
PL064J Sectors
PL032J Sectors
A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
B
48 Mbit (32 Kw x 96)
24 Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
C
48 Mbit (32 Kw x 96)
24 Mbit (32 Kw x 48)
12 Mbit (32 Kw x 24)
D
16 Mbit (4 Kw x 8 and 32 Kw x 31)
8 Mbit (4 Kw x 8 and 32 Kw x 15)
4 Mbit (4 Kw x 8 and 32 Kw x 7)
Bank
PL129J Sectors
CE# Control
1A
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE1#
1B
48 Mbit (32 Kw x 96)
CE1#
2A
48 Mbit (32 Kw x 96)
CE2#
2B
16 Mbit (4 Kw x 8 and 32 Kw x 31)
CE2#
相關(guān)PDF資料
PDF描述
S29PL127J70BFI000 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
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