參數(shù)資料
型號: S29PL032J65BFI150
廠商: SPANSION LLC
元件分類: PROM
英文描述: 2M X 16 FLASH 3V PROM, 65 ns, PBGA56
封裝: 7 X 9 MM, LEAD FREE, FBGA-56
文件頁數(shù): 15/94頁
文件大?。?/td> 949K
代理商: S29PL032J65BFI150
20
S29PL-J
S29PL-J_00_A8 July 29, 2005
Ad van c e
Inf o rmation
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the
high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# (CE1#,CE#2 in PL129J) and RESET#
pins are both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than VIH.) If
CE# (CE1#,CE#2 in PL129J) and RESET# are held at VIH, but not within VIO ± 0.3 V, the device
will be in the standby mode, but the standby current will be greater. The device requires standard
access time (tCE) for read access when the device is in either of these standby modes, before it
is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until
the operation is completed.
ICC3 in DC Characteristics represents the CMOS standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is
independent of the CE#, WE#, and OE# control signals. Standard address access timings pro-
vide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. Note that during automatic sleep mode, OE# must be at VIH be-
fore the device reduces current to the stated sleep mode specification. ICC5 in DC Characteristics
represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When
the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any
operation in progress, tristates all output pins, and ignores all read/write commands for the du-
ration of the RESET# pulse. The device also resets the internal state machine to reading array
data. The operation that was interrupted should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the
device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the
standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset
the Flash memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy)
until the internal reset operation is complete, which requires a time of tREADY (during Embedded
Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is
complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY#
pin is “1”), the reset operation is completed within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristic tables for RESET# parameters and to 18 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins (except for
RY/BY#) are placed in the highest Impedance state
相關(guān)PDF資料
PDF描述
S29PL127J70BFI000 8M X 16 FLASH 3V PROM, 70 ns, PBGA80
S29XS064R0PBHW010 4M X 16 FLASH 1.8V PROM, 80 ns, PBGA44
S2C3R-1-12-H 4000 MHz - 12000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2 dB INSERTION LOSS
S2C5R-1-12-RC 4000 MHz - 18000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 2.8 dB INSERTION LOSS
S2H3R-1H 10 MHz - 1000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.2 dB INSERTION LOSS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S29PL032J70BAI120 功能描述:閃存 32Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BAI122 功能描述:閃存 32MB 閃存 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BAW120 功能描述:閃存 32MB 閃存 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BFI120 功能描述:閃存 32Mb 3V 70ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel
S29PL032J70BFI120(E) 制造商:Spansion 功能描述:Cut Tape