參數(shù)資料
型號(hào)： S29GL032N90BFI32
廠商： SPANSION LLC
元件分類： PROM
英文描述： 2M X 16 FLASH 3V PROM, 90 ns, PBGA48
封裝： 8.15 X 6.15 MM, LEAD FREE, FBGA-48
文件頁數(shù)： 50/81頁
文件大小： 3095K
代理商： S29GL032N90BFI32
54
S29GL-N MirrorBit Flash Family
S29GL-N_01_12 October 29, 2008
Da ta
Sh e e t
Table 10.4 Sector Protection Commands (x8)
Command Sequence
(Notes)
Cyc
le
s
Bus Cycles (Notes 2–5)
1st/8th
2nd/9th
3rd/10th
4th/11th
5th
6th
7th
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Lo
c
k
Reg
ister
Bit
s
Command Set Entry
3
AAA
AA
555
55
AAA
40
Program (Note 6)
2
XXX
A0
XXX
Data
1
00
Data
Command Set Exit
2
XXX
90
XXX
00
Pa
s
w
o
rd
Prot
ect
ion
Command Set Entry
3
AAA
AA
555
55
AAA
60
Program (Note 8)
2
XXX
A0
PWAx
PWDx
8
00
PWD0
01
PWD1
02
PWD2
03
PWD3
04
PWD4
05
PWD5
06
PWD6
07
PWD7
Unlock (Note 10)
11
00
25
00
03
00
PWD0
01
PWD1
02
PWD2
03
PWD3
04
PWD4
05
PWD5
06
PWD6
07
PWD7
00
29
Command Set Exit
2XX
90
XX
00
Non
-V
o
latile
S
e
cto
rP
rot
ecti
on
(P
PB)
Command Set Entry
3
AAA
AA
555
55
AAA
C0
PPB Program (Note 11)
2
XXX
A0
SA
00
All PPB Erase
(Notes 11, 12)
2
XXX
80
00
30
PPB Status Read
1
SA
RD(0)
Command Set Exit
2
XXX
90
XXX
00
Glob
al
V
o
la
ti
le
Secto
rProt
ecti
on
F
re
e
z
e
(P
PB
Loc
k)
Command Set Entry
3
AAA
AA
555
55
AAA
50
PPB Lock Bit Set
2
XXX
A0
XXX
00
PPB Lock Bit Status
Read
1
XXX
RD(0)
Command Set Exit
2
XXX
90
XX
00
V
o
latile
Sector
P
rot
ectio
n
(D
Y
B
)
Command Set Entry
3
AAA
AA
555
55
AAA
E0
DYB Set
2
XXX
A0
SA
00
DYB Clear
2
XXX
A0
SA
01
DYB Status Read
1
SA
RD(0)
Command Set Exit
2
XXX
90
XXX
00
Legend
X = Don’t care.
RA = Address of the memory location to be read.
SA = Sector Address. Any address that falls within a specified sector. See
Tables 8.2–8.8 for sector address ranges.
PWA = Password Address. Address bits A1 and A0 are used to select each 16-
bit portion of the 64-bit entity.
PWD = Password Data.
RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0. If unprotected,
DQ0 = 1.
Notes
1. All values are in hexadecimal.
2. Shaded cells indicate read cycles.
3. Address and data bits not specified in table, legend, or notes are don’t
cares (each hex digit implies 4 bits of data).
4. Writing incorrect address and data values or writing them in the improper
sequence may place the device in an unknown state. The system must
write the reset command to return the device to reading array data.
5. Entry commands are required to enter a specific mode to enable
instructions only available within that mode.
6. No unlock or command cycles required when bank is reading array data.
7. Exit command must be issued to reset the device into read mode; device
may otherwise be placed in an unknown state.
8. Entire two bus-cycle sequence must be entered for each portion of the
password.
9. Full address range is required for reading password.
10. Password may be unlocked or read in any order. Unlocking requires the full
password (all seven cycles).
11. ACC must be at VIH when setting PPB or DYB.
12. “All PPB Erase” command pre-programs all PPBs before erasure to prevent
over-erasure.
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