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參數(shù)資料
| 型號(hào)： | S29GL032N90BFI32 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8.15 X 6.15 MM, LEAD FREE, FBGA-48 |
| 文件頁數(shù)： | 38/81頁 |
| 文件大?。?/td> | 3095K |
| 代理商： | S29GL032N90BFI32 |
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October 29, 2008 S29GL-N_01_12
S29GL-N MirrorBit Flash Family
43
Data
She e t
Any bit in a word cannot be programmed from 0 back to a 1. Attempting to do so may cause the device to
set DQ5=1, or cause DQ7 and DQ6 status bits to indicate the operation was successful. However, a
succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
10.4.2
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to the device faster than using the standard
program command sequence. The unlock bypass command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then
enters the unlock bypass mode. A two-cycle unlock bypass mode command sequence is all that is required to
program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h;
the second cycle contains the program address and data. Additional data is programmed in the same
manner. This mode dispenses with the initial two unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table 10.1 on page 51 and Table 10.3 on page 53
show the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device
then returns to the read mode.
10.4.3
Write Buffer Programming
Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming
operation. This results in faster effective programming time than the standard programming algorithms. The
Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed
by a third write cycle containing the Write Buffer Load command written at the Sector Address in which
programming occurs. The fourth cycle writes the sector address and the number of word locations, minus
one, to be programmed. For example, if the system programs six unique address locations, then 05h should
be written to the device. This tells the device how many write buffer addresses are loaded with data and
therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot
exceed the size of the write buffer or the operation aborts.
The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected
by address bits AMAX–A4. All subsequent address/data pairs must fall within the selected-write-buffer-page.
The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be
loaded in any order.
The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This
means Write Buffer Programming cannot be performed across multiple write-buffer pages.) This also means
that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load
programming data outside of the selected write-buffer page, the operation aborts.
Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter is
decremented for every data load operation. The host system must therefore account for loading a write-buffer
location more than once. The counter decrements for each data load operation, not for each unique write-
buffer-address location. Note also that if an address location is loaded more than once into the buffer, the
final data loaded for that address is programmed.
Once the specified number of write buffer locations are loaded, the system must then write the Program
Buffer to Flash command at the sector address. Any other address and data combination aborts the Write
Buffer Programming operation. The device then begins programming. Data polling should be used while
monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be
monitored to determine the device status during Write Buffer Programming.
The write-buffer programming operation can be suspended using the standard program suspend/resume
commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to
execute the next command.
The Write Buffer Programming Sequence can be aborted in the following ways:
Load a value that is greater than the page buffer size during the Number of Locations to Program step.
Write to an address in a sector different than the one specified during the Write-Buffer-Load command.
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| S29GL032N90DFI023 | 功能描述:IC FLASH 32MBIT 90NS 64BGA 制造商:cypress semiconductor corp 系列:GL-N 包裝:剪切帶（CT） 零件狀態(tài):在售 存儲(chǔ)器類型:非易失 存儲(chǔ)器格式:閃存 技術(shù):FLASH - NOR 存儲(chǔ)容量:32Mb （4M x 8，2M x 16） 寫周期時(shí)間 - 字，頁:90ns 訪問時(shí)間:90ns 存儲(chǔ)器接口:并聯(lián) 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:64-LBGA 供應(yīng)商器件封裝:64 球加強(qiáng)型 BGA（9x9） 標(biāo)準(zhǔn)包裝:1 |
| S29GL032N90FAI030 | 制造商:Spansion 功能描述:IC, FLASH - Trays |
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