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參數(shù)資料
| 型號： | S29GL032N90BFI32 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8.15 X 6.15 MM, LEAD FREE, FBGA-48 |
| 文件頁數(shù)： | 9/81頁 |
| 文件大?。?/td> | 3095K |
| 代理商： | S29GL032N90BFI32 |
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October 29, 2008 S29GL-N_01_12
S29GL-N MirrorBit Flash Family
17
Data
She e t
8.
Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is a latch used to store the commands, along with the address and data information needed to
execute the command. The contents of the register serve as inputs to the internal state machine. The state
machine outputs dictate the function of the device. Table 8.1 lists the device bus operations, the inputs and
control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend
L = Logic Low = VIL
H = Logic High = VIH
VHH = 11.5–12.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. If WP# = VIL, the first or last sector remains protected (for uniform sector devices), and the two outer boot sectors are protected (for boot sector devices). If WP#
= VIH, the first or last sector, or the two outer boot sectors are protected or unprotected as determined by the method described in Write Protect (WP#). All
sectors are unprotected when shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered.)
2. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 10.5 on page 56).
8.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the
BYTE# pin is set at logic 1, the device is in word configuration, DQ0–DQ15 are active and controlled by CE#,
WE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE#, WE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin
is used as an input for the LSB (A-1) address function.
8.2
Requirements for Reading Array Data
All memories require access time to output array data. In a read operation, data is read from one memory
location at a time. Addresses are presented to the device in random order, and the propagation delay through
the device causes the data on its outputs to arrive with the address on its inputs.
The device defaults to reading array data after device power-up or hardware reset. To read data from the
memory array, the system must first assert a valid address on Amax-A0, while driving OE# and CE# to VIL.
WE# must remain at VIH. All addresses are latched on the falling edge of CE#. Data will appear on
DQ15-DQ0 after address access time (tACC), which is equal to the delay from stable addresses to valid output
data. The OE# signal must be driven to VIL. Data is output on DQ15-DQ0 pins after the access time (tOE) has
elapsed from the falling edge of OE#.
See Reading Array Data on page 41 for more information. Refer to Table 15.1 on page 64 for timing
specifications and the timing diagram. Refer to Table 13.1 on page 62 for the active current specification on
reading array data.
Table 8.1 Device Bus Operations
Operation
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
DQ0–
DQ7
DQ8–DQ15
BYTE#
= VIH
BYTE#
= VIL
Read
LL
H
X
AIN
DOUT
DQ8–DQ14
= High-Z,
DQ15 = A-1
Write (Program/Erase)
LH
L
H
XAIN
Accelerated Program
LH
L
H
VHH
AIN
Standby
VCC ± 0.3V
X
VCC ± 0.3V
X
H
X
High-Z
Output Disable
L
H
X
High-Z
Reset
X
L
X
High-Z
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