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參數資料
| 型號： | S29GL032N90BFI32 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
| 封裝： | 8.15 X 6.15 MM, LEAD FREE, FBGA-48 |
| 文件頁數： | 11/81頁 |
| 文件大?。?/td> | 3095K |
| 代理商： | S29GL032N90BFI32 |
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October 29, 2008 S29GL-N_01_12
S29GL-N MirrorBit Flash Family
19
Data
She e t
8.4
Standby Mode
When the system is not reading or writing to the device, it can be placed in to standby mode. In this mode,
current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent
of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO ± 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VIO ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires
standard access time (tACC/tCE) for read access when the device is in either of these standby modes, before
it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
Refer to the DC Characteristics on page 62 for the standby current specification.
8.5
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC
Characteristics on page 62 for the automatic sleep mode current specification.
8.6
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in
progress, output pins go to Hi-Z, and all read/write commands are ignored for the duration of the RESET#
pulse. Program/Erase operations that were interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS ±0.3 V, the device
draws CMOS standby current (ICC5).
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 15.4 on page 66 for the timing
diagram.
8.7
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in a high
impedance state.
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相關代理商/技術參數 |
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| S29GL032N90DFI020 | 功能描述:IC FLASH 32MBIT 90NS 64BGA 制造商:cypress semiconductor corp 系列:GL-N 包裝:托盤 零件狀態(tài):在售 存儲器類型:非易失 存儲器格式:閃存 技術:FLASH - NOR 存儲容量:32Mb （4M x 8，2M x 16） 寫周期時間 - 字，頁:90ns 訪問時間:90ns 存儲器接口:并聯(lián) 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:64-LBGA 供應商器件封裝:64 球加強型 BGA（9x9） 標準包裝:260 |
| S29GL032N90DFI023 | 功能描述:IC FLASH 32MBIT 90NS 64BGA 制造商:cypress semiconductor corp 系列:GL-N 包裝:剪切帶（CT） 零件狀態(tài):在售 存儲器類型:非易失 存儲器格式:閃存 技術:FLASH - NOR 存儲容量:32Mb （4M x 8，2M x 16） 寫周期時間 - 字，頁:90ns 訪問時間:90ns 存儲器接口:并聯(lián) 電壓 - 電源:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C（TA） 安裝類型:表面貼裝 封裝/外殼:64-LBGA 供應商器件封裝:64 球加強型 BGA（9x9） 標準包裝:1 |
| S29GL032N90FAI030 | 制造商:Spansion 功能描述:IC, FLASH - Trays |
| S29GL032N90FAI040 | 功能描述:閃存 32Mb 3V 90ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| S29GL032N90FFI010 | 功能描述:閃存 32Mb 3V 90ns Parallel NOR 閃存 RoHS:否 制造商:ON Semiconductor 數據總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結構:256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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