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參數(shù)資料
| 型號： | S1D15G10D08B000 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | LCD drivers equipped with the liquid crystal drive power circuit |
| 中文描述： | 與液晶驅(qū)動電源電路配備LCD驅(qū)動器 |
| 文件頁數(shù)： | 51/64頁 |
| 文件大小： | 434K |
| 代理商： | S1D15G10D08B000 |
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S1D15G10D08B000
48
EPSON
Rev. 1.0
Ta=
–
40 to +85
°
C, V
DD
=2.6 to 3.6V, V
DDI
=1.7 to 2.6V
Min.
Max.
Unit
Signal
Symbol
Parameter
Measuring conditions
and others
––
A0
t
AH8
t
AW8
Address hold time
Address setup time
10
0
––
––
ns
ns
WR,
RD,CS
t
CYC
t
CYC2
t
CCHW
t
CCHR
t
CCLW
t
CCLR
t
CW8
Write cycle
Read cycle
190
250
140
70
40
170
40
––
––
––
––
––
––
––
ns
ns
ns
ns
ns
ns
ns
––
Control pulse HIGH width (write)
Control pulse HIGH width (read)
Control pulse LOW width (write)
Control pulse LOW width (read)
CS
–
WR, RD time
D0 to D7
t
DS8
t
DH8
Data setup time
Data hold time
10
20
––
––
ns
ns
––
t
ACC8
t
OH8
Read access time
Output disable time
––
5
200
60
ns
ns
C
L
=10 to 100pF
* Rise and fall time of input signal (
t
r
,
t
f
) must be 15 ns maximum.
* All timings must be specified using 30% and 70% of V
DD
-GND as the reference.
*
t
CCLW
and
t
CCLR
are specified by the duration during which CS as well as WR and RD are LOW.
* A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
Ta=
–
40 to +70
°
C, V
DD
=V
DDI
=2.9V
±
3%
Max.
Unit
Measuring conditions
Signal
Symbol
Parameter
Min.
and others
––
A0
t
AH8
t
AW8
Address hold time
Address setup time
10
0
––
––
ns
ns
WR,
RD,CS
t
CYC
t
CYC2
t
CCHW
t
CCHR
t
CCLW
t
CCLR
t
CW8
Write cycle
Read cycle
150
250
110
70
35
170
35
––
––
––
––
––
––
––
ns
ns
ns
ns
ns
ns
ns
*
1
Control pulse HIGH width (write)
Control pulse HIGH width (read)
Control pulse LOW width (write)
Control pulse LOW width (read)
CS
–
WR, RD time
D0 to D7
t
DS8
t
DH8
Data setup time
Data hold time
10
20
––
––
ns
ns
––
t
ACC8
t
OH8
Read access time
Output disable time
––
5
200
60
ns
ns
C
L
=10 to 100pF
*1
t
CYC
is specified by
t
CCHW
+
t
CCLW
+
t
r
+
t
f
.
*2 All timings must be specified using 30% and 70% of V
DD
-GND as the reference.
*3
t
CCLW
and
t
CCLR
are specified by the duration during which CS as well as WR and RD are LOW.
*4 A0 timing is specified by the duration during which CS as well as WR and RD are LOW.
*5 Rise and fall time of input signal (
t
r
,
t
f
) must be 15 ns maximum.
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