
S1D15G10D08B000
26
EPSON
Rev. 1.0
Table 8.11.3 shows the theoretical expression of respective potentials. Since these are theoretical values, they can differ
from actual voltages depending on load on the liquid crystal.
Table 8.11.3 Theoretical Expression of Potentials
Signal name
Theoretical expression
(relative to GND = 0V)
2
×
(V
2
–
GND)
4/3
×
(V
1
–
GND)
Output from voltage regulator
2/3
×
(V
1
–
GND)
1/3
×
(V
1
–
GND)
0V
–
(V
1
–
GND)
Theoretical expression
(relative to V
C
= 0V)
2
×
(V
C
–
GND)
V
C
–
GND
1/2
×
(V
C
–
GND)
0V
–
1/2
×
(V
C
–
GND)
–
(V
C
–
GND)
–
2
×
(V
C
–
GND)
V
3
V
2
V
1
V
C
MV
1
GND(MV
2
)
MV
3
Fig. 8.11.2 Relation between Capacitors and Voltage Step-up
8.11.4 Voltage Regulator Circuit
The voltage regulator circuit generates the liquid crystal drive voltage V
1
using V
CSL
from the primary booster circuit.
S1D15G10 incorporates the high-precision constant voltage source, 64-step electronic volume control function and
resistor to regulate V
1
voltage. The voltage regulator circuit covers a wider temperature range with fewer numbers of
parts thanks to the temperature gradient control function as well as the temperature sensing function.
However, capacitors may be required for voltage regulation between V
1
and GND pins due to the load of LCD panel.
Insert the capacitors, if necessary, by observing the voltage waveforms and current consumption.
(A) Built-in Resistor for V
1
Voltage Regulation
Using this resistor and the electronic volume control function allows you to control the liquid crystal drive voltage V
1
to an optimum level for the LCD panel with the command alone, without resorting to external resistors.
V
1
output voltage can be determined from Equation A-1 as long as the relation V
1
< V
CSL
is met.
However, set the voltage of V
1
by allowing for a drop in the voltage due to load, so that it becomes at or below 80 %
of V
CSL
.
Rb
Ra
Ra
218
Note: V
REG
is the constant voltage source inside the IC. It is 1.2V (Typ.) at Ta = 25
°
C.
V
V
Rb
V
EV
REG
1
1
1
1
2
=
+
=
+
+
–
α
(Equation A-1)
8.11.3 Primary Booster Circuit
The built-in booster circuit double the voltage of V
DD2
-GND.
V
DD2
-GND voltage is double by capacitor C connected across CAP1+ and CAP1 as well as V
CSL
and GND (or V
DD2
),
and then output at V
CSL
pin.
Fig. 8.11.2 shows how the voltage is stepped up by the capacitors connected.
V
DD2
GND
V
CSL=
2xV
DD2
C
C
GND or V
DD2
V
CSL
CAP1
–
CAP1+
+
+