參數(shù)資料
型號： S1D15G10D08B000
廠商： 愛普生（中國）有限公司
英文描述： LCD drivers equipped with the liquid crystal drive power circuit
中文描述： 與液晶驅(qū)動電源電路配備LCD驅(qū)動器
文件頁數(shù)： 25/64頁
文件大?。?/td> 434K
代理商： S1D15G10D08B000
S1D15G10D08B000
22
EPSON
Rev. 1.0
8.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the
DDRAM to display image on the LCD.
You can specify a scope of the page address (start and end page) with PASET (page address set) command. When the
page-direction scan is specified with DATCTL (data control) command and the addresses are incremented from the start
up to the end page, the column address is incremented by 1 and the page address returns to the start page.
The DDRAM supports up to 132 lines, and thus the total page becomes 132.
In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page
address is returned to the start page.
Using the address normal/inverse parameter of DATCTL command allows you to inverse the correspondence between
the DDRAM address and common output.
8.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify
a scope of the column address (start and end column) using CASET (column address set). When the column-direction
scan is specified with DATCTL command and the addresses are incremented from the start to the end up to the end
column, the page address is incremented by 1 and the column address returns to the start column.
In the read operation, too, the column address is automatically incremented by 1 and returns to the start page as the end
column is reached.
Just like the page address control circuit, using the column address normal/inverse parameter of DATCTL command
enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement
relaxes restrictions in the chip layout on the LCD module.
8.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU’s read or write of the DDRAM
is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM while
the LCD is turned on does not cause troubles such as flicking of the display images.
8.3.5 Block Address Circuit
This circuit associates pages on the DDRAM with COM output. S1D15G10 processes signals for the liquid crystal
display on 4-page basis (block basis). Thus, when specifying a specific area in the area scroll display or partial display,
you must designate it in block.
8.3.6 Display Data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since
DISNOR/DISINV (display normal/inverse) and DISON/DISOFF (display on/display off) commands are used to
control data in the latch circuit alone, they do not modify data in the DDRAM.
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