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參數(shù)資料
| 型號： | S1D15G10D08B000 |
| 廠商： | 愛普生（中國）有限公司 |
| 英文描述： | LCD drivers equipped with the liquid crystal drive power circuit |
| 中文描述： | 與液晶驅(qū)動(dòng)電源電路配備LCD驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 18/64頁 |
| 文件大?。?/td> | 434K |
| 代理商： | S1D15G10D08B000 |
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S1D15G10D08B000
Rev. 1.0
EPSON
15
8.2
S1D15G10 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the
bus holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle
is dummy and the data read in the dummy cycle is held by the bus holder, and then it is read from the bus holder to the
system bus in the succeeding read cycle. Fig. 8.2.1 illustrates these relations.
Access to DDRAM and Internal Registers
* There is a restriction in the read sequence of the DDRAM. Namely, the data at the specified address is not output
in the first data read conducted immediately after the memory read command (dummy read). It is read in the second
data read.
Fig. 8.2.1
* Write operation
* Read operation
A0
WR
RD
External pulse
Data Read
signal
Bus holder
MPU
RAM data
RAM data
Command write
Dummy read
Data read
Internal
Command
A0
tcyc
WR
DATA
Data write
signal
Bus holder
MPU
Command write
Data write
Data write
Internal
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