參數(shù)資料
型號: S1D13700
廠商: 愛普生(中國)有限公司
英文描述: Embedded Memory Graphics LCD Controller
中文描述: 嵌入式內(nèi)存圖形液晶顯示控制器
文件頁數(shù): 51/134頁
文件大?。?/td> 1000K
代理商: S1D13700
Epson Research and Development
Vancouver Design Center
Page 51
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
Note
Screen Origin Compensation shifts the character font down by one pixel row. If the bot-
tom pixel row of the font is at the bottom of the Screen Block, that row disappears when
REG[00h] bit 5 = 0. To compensate for the bad visual effect, SL can be increased by
one.
bit 2
Character Height (M2)
This bit selects the height of the character bitmaps. It is possible to display characters
greater than 16 pixels high by creating a bitmap for each portion of each character and
using graphics mode to reposition them.
When this bit = 0, the character height is 8 pixels.
When this bit = 1, the character height is 16 pixels.
bit 1
Reserved
The default value for this bit is 0.
bit 0
Character Generator Select (M0)
This bit determines whether characters are generated by the internal character generator
ROM (CGROM) or character generator RAM (CGRAM). The CGROM contains 160,
5x7 pixel characters which are fixed at fabrication. The CGRAM can contain up to 256
user-defined characters which are mapped at the CG Start Address (REG[1Ah] -
REG[19h]). However, when the CGROM is used, the CGRAM can only contain up to 64,
8x8 pixel characters.
When this bit = 0, the internal CGROM is selected.
When this bit = 1, the internal CGRAM is selected.
Table 10-2 LCD Parameter Summary
Parameter
Single Panel (REG[00h] bit 3 = 0)
Dual Panel (REG[00h] bit 3 = 1)
REG[00h] bit 5 = 1 (IV)
REG[00h] bit 5 = 0 (IV)
REG[00h] bit 5 = 1 (IV)
REG[00h] bit 5 = 0 (IV)
C/R
REG[03h] bits 7-0
REG[03h] bits 7-0
REG[03h] bits 7-0
REG[03h] bits 7-0
TC/R
REG[04h] bits 7-0
REG[04h] bits 7-0
REG[04h] bits 7-0
REG[04h] bits 7-0
L/F
REG[05h] bits 7-0
REG[05h] bits 7-0
REG[05h] bits 7-0
REG[05h] bits 7-0
SL1
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
(See Note)
[REG[05h] bits 7-0 + 1]
÷
2 - 1
[REG[05h] bits 7-0 + 1]
÷
2 - 1
SL2
00h to REG[05h] bits 7-0
00h to REG[05h] bits 7-0
(See Note)
[REG[05h] bits 7-0 + 1]
÷
2 - 1
[REG[05h] bits 7-0 + 1]
÷
2 - 1
SAD1
First screen block (Start Address = REG[0Bh], REG[0Ch])
SAD2
Second screen block (Start Address = REG[0Eh], REG[0Fh])
SAD3
Third screen block (Start Address = REG[11h], REG[12h])
SAD4
Invalid
Fourth screen block (Start Address = REG[13h], REG[14h])
Cursor
movement
range
Continuous movement over whole screen
Above-and-below configuration: continuous movement over
whole screen
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