參數(shù)資料
型號(hào): S1D13700
廠商: 愛(ài)普生(中國(guó))有限公司
英文描述: Embedded Memory Graphics LCD Controller
中文描述: 嵌入式內(nèi)存圖形液晶顯示控制器
文件頁(yè)數(shù): 20/134頁(yè)
文件大?。?/td> 1000K
代理商: S1D13700
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Page 20
Epson Research and Development
Vancouver Design Center
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
A0
I
16
CI
HIOVDD
Z
System Address pin 0.
For Direct addressing mode, this pin is used for system
address bit 0.
For Indirect addressing mode, this pin in conjunction with RD#
and WR# determines the type of data present on the data bus.
D[7:0]
IO
44-47,
49-52
CB2
HIOVDD
0 or Z
System data bus pins 7-0.
These tristate input/output data pins must be connected to the
microprocessor data bus.
CNF[1:0]
I
57, 56
SI
HIOVDD
Z
These input pins are used for configuration of the FPSHIFT clock
cycle time and must be connected to either HIOVDD or VSS. For
further information, see Section 5.3, “Summary of Configuration
Options” on page 24.
CNF[3:2]
I
59, 58
SI
HIOVDD
Z
These input pins select the host bus interface (microprocessor
interface) and must be connected to either HIOVDD or VSS. The
S1D13700 supports Generic processors (such as the 8085 and
Z80), the MC68K family of processors (such as the 68000) and
the M6800 family of processors (such as the 6800). For further
information, see Section 5.3, “Summary of Configuration Options”
on page 24.
CNF4
I
60
SI
HIOVDD
Z
This input pin selects the microprocessor addressing mode and
must be connected to either HIOVDD or VSS. The S1D13700
supports both Direct and Indirect addressing modes. For further
information, see Section 5.3, “Summary of Configuration Options”
on page 24.
RD#
I
41
SI
HIOVDD
Z
This input pin has multiple functions.
When the Generic host bus interface is selected, this pin is the
active-LOW read strobe (RD#). The S1D13700 data output
buffers are enabled when this signal is low.
When the M6800 host bus interface is selected, this pin is the
active-high enable clock (E). Data is read from or written to the
S1D13700 when this clock goes high.
When the MC68K host bus interface is selected, this pin is the
active-low lower data strobe (LDS#). Data is read from or
written to the S1D13700 when this signal goes low.
WR#
I
42
SI
HIOVDD
Z
This input pin has multiple functions.
When the Generic host bus interface is selected, this signal is
the active-low write strobe (WR#). The bus data is latched on
the rising edge of this signal.
When the M6800 host bus interface is selected, this signal is
the read/write control signal (R/W#). Data is read from the
S1D13700 if this signal is high, and written to the S1D13700 if
it is low.
When the MC68K host bus interface is selected, this signal is
the read/write control signal (RD/WR#). Data is read from the
S1D13700 if this signal is high, and written to the S1D13700 if
it is low.
CS#
I
43
SI
HIOVDD
Z
Chip select.
This active-low input enables the S1D13700. It is usually
connected to the output of an address decoder device that maps
the S1D13700 into the memory space of the controlling
microprocessor.
Table 5-2 Host Interface Pin Descriptions
Pin Name
Type
Pin #
Cell
Power
RESET#
State
Description
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