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    參數(shù)資料
    型號： S1D13700
    廠商： 愛普生（中國）有限公司
    英文描述： Embedded Memory Graphics LCD Controller
    中文描述： 嵌入式內(nèi)存圖形液晶顯示控制器
    文件頁數(shù)： 22/134頁
    文件大?。?/td> 1000K
    代理商： S1D13700
    Page 22
    Epson Research and Development
    Vancouver Design Center
    S1D13700
    X42A-A-001-00
    Hardware Functional Specification
    Issue Date: 2004/01/06
    Revision 1.0
    5.2.2 LCD Interface
    In order to provide effective low-power drive for LCD matrixes, the S1D13700 can directly
    control both the X and Y-drivers using an enable chain.
    Table 5-3 LCD Interface Pin Descriptions
    Pin Name
    Type
    Pin #
    Cell
    Power
    RESET#
    State
    Description
    FPDAT[3:0]
    (XD[3:0])
    O
    18-21
    OB2T
    NIOVDD
    X
    These output pins are the 4-bit X-driver (column drive) data
    outputs and must be connected to the inputs of the X-driver chips.
    FPSHIFT
    (XSCL)
    O
    23
    OB2T
    NIOVDD
    X
    The falling edge of FPSHIFT latches the data on FPDAT[3:0] into
    the input shift registers of the X-drivers. To conserve power, this
    clock is stopped between FPLINE and the start of the following
    display line.
    XECL
    O
    24
    OB2T
    NIOVDD
    X
    The falling edge of XECL triggers the enable chain cascade for the
    X-drivers. Every 16th clock pulse is output to the next X-driver.
    FPLINE
    (LP)
    O
    26
    OB2T
    NIOVDD
    X
    FPLINE latches the signal in the X-driver shift registers into the
    output data latches. FPLINE is a falling edge triggered signal, and
    pulses once every display line. FPLINE must be connected to the
    Y-driver shift clock on LCD modules.
    MOD
    (WF)
    O
    27
    OB2T
    NIOVDD
    X
    This output pin is the LCD panel backplane bias signal. The MOD
    period is selected using the SYSTEM SET command.
    YSCL
    O
    29
    OB2T
    NIOVDD
    X
    The falling edge of YSCL latches the data on FPFRAME into the
    input shift registers of the Y-drivers. YSCL is not used with driver
    ICs which use FPLINE as the Y-driver shift clock.
    FPFRAME
    (YD)
    O
    30
    OB2T
    NIOVDD
    X
    This output pin is the data pulse output for the Y drivers. It is active
    during the last line of each frame, and is shifted through the Y
    drivers one by one (by YSCL), to scan the display’s common
    connections.
    YDIS
    O
    31
    OB2T
    NIOVDD
    L
    This output pin is the power-down output signal. YDIS is high while
    the display drive outputs are active. YDIS goes low one or two
    frames after the power save command is written to the S1D13700.
    All Y-driver outputs are forced to an intermediate level (de-
    selecting the display segments) to blank the display. In order to
    implement power-down operation in the LCD unit, the LCD power
    drive supplies must also be disabled when the display is disabled
    by YDIS.
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    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    S1D13700F01A100 功能描述:顯示驅(qū)動器和控制器 LCD CONTROLLER RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel
    S1D13700F02A100 功能描述:顯示驅(qū)動器和控制器 (QVGA) 320x240 B/W STN LCD C RoHS:否 制造商:Panasonic Electronic Components 工作電源電壓:2.7 V to 5.5 V 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Reel
    S1D13701F00A100 功能描述:LCD 驅(qū)動器 Organic EL Controller RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube
    S1D13702F00A100 功能描述:LCD 驅(qū)動器 Organic EL Controller RoHS:否 制造商:Maxim Integrated 數(shù)位數(shù)量:4.5 片段數(shù)量:30 最大時鐘頻率:19 KHz 工作電源電壓:3 V to 3.6 V 最大工作溫度:+ 85 C 最小工作溫度:- 20 C 封裝 / 箱體:PDIP-40 封裝:Tube
    S1D13704F00A 制造商:EPSON 制造商全稱:EPSON 功能描述:LCD Controller ICs
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