參數(shù)資料
型號: S1D13700
廠商: 愛普生(中國)有限公司
英文描述: Embedded Memory Graphics LCD Controller
中文描述: 嵌入式內(nèi)存圖形液晶顯示控制器
文件頁數(shù): 126/134頁
文件大?。?/td> 1000K
代理商: S1D13700
Page 126
Epson Research and Development
Vancouver Design Center
S1D13700
X42A-A-001-00
Hardware Functional Specification
Issue Date: 2004/01/06
Revision 1.0
17 Power Save Mode
The S1D13700 supports a power save mode that places it into a power efficient state. Power
save mode is controlled by the Power Save Mode Enable bit, REG[08h] bit 0. The
S1D13700 enters power save mode at least one blank frame after the enable bit is set.
When power save mode is enabled, blank data is sent to the X-drivers, and the Y-drivers
have their bias supplies turned off by the YDIS signal. Using the YDIS signal to disable the
Y-drivers guards against any spurious displays. The internal registers of the S1D13700
maintain their values during the power save state and the display memory control pins
maintain their logic levels to ensure that the display memory is not corrupted.
The S1D13700 is removed from power save mode by writing a 0 the Power Save Mode
Enable bit, REG[08h] bit 0. However, after disabling power save mode, one dummy write
to any register must be performed for direct addressing mode, and at least two dummy
writes must be performed for indirect addressing mode.
For indirect addressing mode, the POWER SAVE command has no parameter bytes. For
indirect addressing mode, the SYSTEM SET command exits power save mode.
1. The YDIS signal goes LOW between one and two frames after the power save com-
mand is received. Since YDIS forces all display driver outputs to go to the deselected
output voltage, YDIS can be used as a power down signal for the LCD unit. This can
be done by having YDIS turn off the relatively high power LCD drive supplies at the
same time as it blanks the display.
2. Since all internal clocks in the S1D13700 are halted while power save mode is en-
abled, a DC voltage is applied to the LCD panel if the LCD drive supplies remain on.
If reliability is a prime consideration, turn off the LCD drive supplies before issuing
the power save command.
3. The bus lines become high impedance when power save mode is enabled. If the bus is
required to be a known state, pull-up or pull-down resistors can be used.
Table 17-1 State of LCD Pins During Power Save Mode
LCD Pin
YDIS
FPFRAME
YSCL
MOD
FPLINE
XECL
FPSHIFT
FPDAT[3:0]
WAIT#
DB[7:0]
XCD1
State During Display Off
Low
Low
High
Low
Low
Low
Low
Low
Hi-Z
Hi-Z
High
State During Power Save Mode
Low
Low
High
Low
Low
Low
Low
Low
Hi-Z
Hi-Z
High
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