參數(shù)資料
型號： S1D13700
廠商： 愛普生（中國）有限公司
英文描述： Embedded Memory Graphics LCD Controller
中文描述： 嵌入式內(nèi)存圖形液晶顯示控制器
文件頁數(shù)： 31/134頁
文件大小： 1000K
代理商： S1D13700
Epson Research and Development
Vancouver Design Center
Page 31
Hardware Functional Specification
Issue Date: 2004/01/06
S1D13700
X42A-A-001-00
Revision 1.0
1.
2.
3.
Ts
t4min
t11max = 1Ts + 5 (for 3.3V)
= 1Ts + 7 (for 5.0V)
t12max = 4Ts + 18 (for 3.3V)
= 4Ts + 20 (for 5.0V)
t13min = 6Ts (for a read cycle followed by a read or write cycle)
= 7Ts + 2 (for a write cycle followed by a write cycle)
= 10Ts + 2 (for a write cycle followed by a read cycle)
t15min = 1Ts (for a read cycle followed by a read or write cycle)
= 2Ts + 2 (for a write cycle followed by a write cycle)
= 5Ts + 2 (for a write cycle followed by a read cycle)
t16max = 4Ts + 2
= System clock period
= 2Ts + 5
4.
5.
6.
7.
Table 7-2 Generic Bus Direct/Indirect Interface with WAIT# Timing
Symbol
Parameter
3.3 Volt
5.0 Volt
Units
Min
Max
15
10
14
Min
Max
15
10
14
t1
CS# setup time
5
5
ns
t2
AB[15:0] setup time
5
5
ns
t3
WR#, RD# falling edge to WAIT# driven low
2
2
ns
t4
DB[7:0] setup time to WR# rising edge (write cycle)
Note 2
Note 2
ns
t5
RD# falling edge to DB[7:0] driven (read cycle)
3
3
ns
t6
CS# hold time
7
7
ns
t7
AB[15:0] hold time
7
7
ns
t8
RD#, WR# rising edge to WAIT# high impedance
2
2
ns
t9
DB[7:0] hold time from WR# rising edge (write cycle)
5
5
ns
t10
DB[7:0] hold time from RD# rising edge (read cycle)
3
3
ns
t11
WAIT# rising edge to valid Data if WAIT# is used
Note 3
Note 3
ns
t12
RD# falling edge to valid Data if WAIT# is not used
Note 4
Note 7
Note 4
Note 7
ns
t13
RD#, WR# cycle time
Note 5
Note 5
ns
t14
RD#, WR# pulse active time
5
5
Ts
t15
RD#, WR# pulse inactive time
Note 6
Note 6
ns
t16
WAIT# pulse active time
ns
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