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參數資料
| 型號： | S1C6P366D0A0100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, FLASH, 4.1 MHz, MICROCONTROLLER, UUC102 |
| 封裝： | DIE-102 |
| 文件頁數： | 73/84頁 |
| 文件大?。?/td> | 1740K |
| 代理商： | S1C6P366D0A0100 |
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S1C6P366 TECHNICAL MANUAL
EPSON
65
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Programmble Timer)
Counter
input clock
Counter data
n
n-1
n-2
n-3
K13 input
2,048 Hz
When PLPOL register is set to "0"
Fig. 4.9.3.2.2 Count down timing with noise rejecter
The operation of the event counter mode is the same as the timer mode except it uses the K13 input as
the clock.
Refer to Section 4.9.3.1, "Setting of initial value and counting down" for basic operation and control.
4.9.3.3 Setting of input clock in timer mode
The 16 bit programmable timer include a prescaler. The prescalers generate the input clock for this
programmable timer by dividing the source clock supplied from the OSC1 or OSC3 oscillation circuit.
The source clock (OSC1 or OSC3) and the division ratio of the prescaler can be selected with software.
The set input clock is used for the count clock during operation in the timer mode. When the 16 bit
programmable timer is used in the event counter mode, the following settings become invalid.
The input clock is set in the following sequence.
(1) Selection of source clock
Select the source clock input to the prescaler from either OSC1 or OSC3. This selection is done using
the source clock selection register CKSEL0 (timer 0); when "0" is written to the register, OSC1 is
selected and when "1" is written, OSC3 is selected.
When the OSC3 oscillation clock is selected for the clock source, it is necessary to turn the OSC3
oscillation ON, prior to using the programmable timer. However the OSC3 oscillation circuit requires
a time interval of at least 5 msec from turning the circuit ON until the oscillation stabilizes. Therefore,
allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable
timer. Refer to Section 4.3, "Oscillation Circuit", for the control and notes of the OSC3 oscillation
circuit.
At initial reset, the OSC3 oscillation circuit is set in the OFF state.
(2) Selection of prescaler division ratio
Select the division ratio for the prescaler from among 4 types. This selection is done using the
prescaler division ratio selection registers PTPS00/PTPS01 (timer 0). Table 4.9.3.3.1 shows the corre-
spondence between the setting value and the division ratio.
Table 4.9.3.3.1 Selection of prescaler division ratio
PTPS01
1
0
PTPS00
1
0
1
0
Prescaler division ratio
Source clock / 256
Source clock / 32
Source clock / 4
Source clock / 1
By writing "1" to the register PTRUN0 (timer 0), the prescaler inputs the source clock and outputs the
clock divided by the selected division ratio. The counter starts counting down by inputting the clock.
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